Senior Digital Design Engineer, IP and Methodology (AI)

Location: San Jose, California, United States

Base salary: $135,000–$195,000 per year, depending on experience, level, and business need. The role may also include discretionary bonuses, incentives, and benefits.

Company

hirify.global develops semiconductor-based connectivity solutions and software for rack-scale AI infrastructure, integrating technologies such as CXL, Ethernet, NVLink, PCIe, and UALink.

What you will do

• Own RTL implementation of complex digital designs from micro-architecture through sign-off.
• Design CPU subsystems and embedded processor interfaces for high-performance connectivity products.
• Develop security-focused digital blocks, including secure boot, cryptographic engines, and trusted execution environments.
• Collaborate with verification, physical design, and DFT teams to review test plans, debug issues, achieve timing closure, and implement DFT features.
• Develop scripting and automation that improves ASIC design methodology, infrastructure, productivity, and design quality.

Requirements

• Bachelor’s degree in Electrical Engineering or an equivalent qualification.
• 3+ years of experience developing SoC or silicon products in server, storage, and/or networking markets.
• Production expertise in RTL coding with SystemVerilog and Python, plus synthesis using Synopsys or Cadence tools.
• Experience with CPU subsystem design or embedded processor integration using RISC-V, ARM, or similar architectures.
• Understanding of silicon security fundamentals, including secure boot, root of trust, and cryptographic implementations.
• Experience with clocking, CDC, and RDC methodologies.

Nice to have

• Experience designing or integrating security IP such as cryptographic accelerators, secure enclaves, or key management.
• Familiarity with PCIe Gen 6/7, Ethernet, UALink, or UCI protocols.
• Experience with CMOS nodes of 7nm or smaller and exposure to embedded firmware or secure firmware boot flows.
• Experience with functional and formal verification at block and chip level, including UVM-based methodologies.

Culture & Benefits

• Work on connectivity solutions that support hyperscale data centers and rack-scale AI infrastructure.
• Collaborate with teams spanning design, verification, physical design, and DFT.
• Discretionary bonus, incentives, and benefits may be available.
• Applications are encouraged from candidates with diverse backgrounds and experiences.