Senior or Staff Digital Design Engineer (ASIC)

Location: Hybrid, requiring 3 days per week onsite at HQs in Vancouver, WA or Chandler, AZ; remote flexibility may be considered for exceptional candidates in Silicon Valley, CA.

Salary: $150,000–$200,000 annual base salary for Member of Technical Staff.

Company

hirify.global is a well-funded semiconductor startup developing chiplet power delivery technology for high-performance processors, AI, and advanced computing.

What you will do

• Develop microarchitecture and synthesizable RTL for complex digital blocks, subsystems, and SoC components.
• Evaluate performance, power, area, and testability tradeoffs and participate in design reviews.
• Integrate RTL into larger SoC environments and support lint, CDC/RDC, synthesis, LEC, and design quality checks.
• Collaborate with physical design teams on implementation issues, timing constraints, timing closure, and ECOs.
• Support silicon bring-up, validation, post-silicon debug, and issue resolution throughout the development lifecycle.
• Work with verification, DFT, physical implementation, firmware, systems, architecture, and technical leadership teams; mentor junior engineers at Staff level.

Requirements

• Ability to work onsite 3 days per week in Vancouver, WA or Chandler, AZ; exceptional remote candidates in Silicon Valley, CA may be considered.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 6+ years of digital IC design experience.
• Hands-on RTL development with Verilog or SystemVerilog and experience designing digital blocks for complex SoCs or ASICs.
• Strong understanding of RTL design, microarchitecture, SoC integration, on-chip interfaces, clocking, resets, CDC/RDC, synthesis, physical implementation, SDC constraints, and timing closure.
• Experience with industry-standard Synopsys and/or Cadence EDA tools, plus strong debugging and collaboration skills.

Nice to have

• DFT methodologies, including scan insertion and MBIST.
• Logic equivalence checking, static timing analysis, UPF/CPF, or formal verification.
• Experience with advanced semiconductor process nodes, silicon bring-up, and post-silicon debug.

Culture & Benefits

• Collaborative startup environment with direct impact on product development.
• Stock option grant.
• Comprehensive health, dental, and vision benefits.
• 401(k) plan.