Lead RTL/FPGA Design Engineer (Aerospace)

Location: Remote within the United States, with occasional travel to the Mountain View office.

Company

hirify.global develops laser communications technology and temporospatial software-defined networking platforms for aerospace, satellite, airborne, cislunar, and deep-space communications.

What you will do

• Own end-to-end FPGA modem development from architecture and micro-architecture through silicon bring-up and bench testing.
• Develop synthesizable RTL in VHDL or SystemVerilog for DSP blocks including equalization, carrier recovery, and timing recovery.
• Integrate high-throughput Forward Error Correction engines and high-speed interfaces into the modem architecture.
• Translate DSP algorithm models into fixed-point RTL and validate implementations through test benches and vector matching.
• Perform power, performance, and area analysis, verification, debugging, synthesis, and static timing closure.
• Collaborate with system architects, DSP developers, and firmware/software engineers on hardware/software partitioning, interfaces, and system integration.

Requirements

• Active security clearance or eligibility to obtain one.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 5+ years of hands-on RTL design experience for high-speed digital communications or related systems.
• Strong logic design knowledge and high-quality RTL coding skills in VHDL or SystemVerilog.
• Experience defining micro-architectures, preparing detailed design specifications, and ensuring compliance with relevant standards.
• Eligibility to access U.S. export-controlled information under ITAR/EAR requirements.

Nice to have

• End-to-end FPGA communications system delivery from architecture through hardware validation.
• Experience with complex DSP functions, FEC engines such as LDPC or Reed-Solomon, and coherent modem or FSO communications architectures.
• Experience converting Matlab or C++ system models into fixed-point RTL and performing vector matching.
• Familiarity with ASIC/FPGA synthesis, place and route, static timing analysis, low-power design, and multi-gigabit interfaces.
• Experience with MAC or adjacent digital interface layers, SoC architectures, embedded processors, hardware/software protocols, Python, Perl, or TCL.

Culture & Benefits

• Work on aerospace communications technology and national security programs.
• Flexible remote and in-office working arrangements, with this role primarily remote in the United States.
• Professional development and career advancement opportunities.
• Collaborative, supportive, and inclusive workplace.
• Benefits include 401(k), dental, vision, health and life insurance, paid time off, and equity options.