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8 часов назад

Senior FPGA Developer (SystemVerilog)

Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Germany
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior FPGA Developer (SystemVerilog) (Quantum Key Distribution): Building and verifying end-to-end RTL architectures, deterministic pipelines, and high-rate interfaces for a Quantum Key Distribution system with an accent on AMD/Xilinx FPGA implementation, timing closure, and hardware bring-up. Focus on integrating DDR3/DDR4, PCIe/DMA, and Ethernet/SFP paths, establishing automated verification and CI, and delivering reproducible versioned bitstreams.

Location: Germany, hybrid; on-site work at the Munich or Potsdam offices is required when needed. Applicants must have the right to work in Germany.

Company

hirify.global is a quantum technology company developing quantum-as-a-service, quantum computing, hybrid quantum systems, and quantum-enabled security solutions.

What you will do

  • Own the SystemVerilog RTL architecture and implementation for AMD/Xilinx Artix-7 and Kintex UltraScale platforms using Vivado.
  • Integrate DDR3/DDR4 controllers, PCIe endpoints and DMA, Ethernet/SFP paths, and third-party MAC/PCS IP.
  • Build deterministic acquisition, timing, sifting, packetization, buffering, alignment, clocking, CDC/reset, and low-level protocol layers.
  • Define AXI/AXI-Stream boundaries and register maps for software and firmware integration.
  • Establish verification and CI for lint, simulation, synthesis, implementation, regressions, artifact archiving, and hardware-in-the-loop smoke tests.
  • Lead board bring-up, timing closure, ILA-based debugging, bitstream release management, and mentoring of a junior engineer.

Requirements

  • 5+ years of production FPGA development on AMD/Xilinx platforms and expert SystemVerilog RTL skills.
  • Strong experience with XDC constraints, timing closure, CDC/reset methodology, floorplanning, and report analysis.
  • Hands-on experience with DDR3/DDR4, PCIe endpoints/DMA, Ethernet/SFP, and third-party MAC/PCS IP.
  • Strong verification background with self-checking testbenches, regression testing, and ModelSim/Questa.
  • Experience with HDL CI using Tcl, Make, or Python, plus linting, artifact/version management, board bring-up, and ILA-based debug.
  • Written and spoken English, the right to work in Germany, and eligibility for a U.S. Secret, EU SECRET, or equivalent national security clearance are required. Visa sponsorship is not provided.

Nice to have

  • AXI4/AXI-Stream expertise, DMA performance tuning, or formal verification experience.
  • Python/Tcl automation and CI systems such as GitHub Actions or Jenkins.
  • MicroBlaze/Zynq experience and low-level firmware or C driver collaboration.
  • Proven delivery on Artix-7 or Kintex UltraScale with Vivado.

Culture & Benefits

  • Flexible hybrid and remote working arrangements within the role’s location requirements.
  • Work with quantum technology specialists on quantum-enabled security and other advanced scientific applications.
  • Personal development planning with clear advancement goals.
  • Competitive salary and a diverse, supportive, professional environment.
  • Trust, excellence, continuous improvement, innovation, and initiative are encouraged.

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