Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Зарплата и рынок
Мало
$75к-232к/год
$140к$150кмедиана$180к
По похожим ролям (50) ~ $150к/год
На СНГ рынке: $1.9к/мес ($1.8к - $2.5к)
65
Средняя вакансия
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Роль четко определена с ясными обязанностями, но зарплата ниже рыночной средней, что может снизить привлекательность.
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Низкая зарплатаЧетко определенная рольСильная корпоративная культура
Оценка от Hirify AI
Мэтч & Сопровод
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Principal Engineer - Analog Design (IP Tech Lead) (Mixed-Signal IP/SoC): Leading the end-to-end development, licensing, integration, and silicon validation of mixed-signal IPs for advanced SoC projects with an accent on high-speed SERDES, PLLs, PVT sensors, IOs, and system-level clocking. Focus on architecting IP integration, resolving cross-functional validation issues, and debugging and characterizing silicon after fabrication.
Location: Chandler, Arizona, United States; travel required 0%–25%; work is performed indoors with approximately 80% sitting, 10% standing, and 10% walking.
Annual base salary: $75,000–$232,000, plus restricted stock units and quarterly bonus payments.
Company
hirify.global is a global semiconductor company developing analog, mixed-signal, and other technologies for products that interface with the outside world.
What you will do
Provide end-to-end technical leadership for mixed-signal IPs across advanced SoC projects, including licensing, integration, and silicon validation support.
Define and review IP interface specifications, integration guidelines, and verification plans.
Evaluate, select, and license third-party and internally developed IPs; collaborate with vendors to customize solutions and finalize Statements of Work.
Architect and drive integration of mixed-signal IPs into SoC designs, including review and sign-off of system-level clocking needs for electrical compliance.
Collaborate with design, verification, physical design, and test engineering teams to resolve integration and validation issues.
Oversee and participate in post-fabrication silicon validation, characterization, and debug while tracking industry standards and best practices.
Requirements
Bachelor’s degree in electrical engineering or a related field with a strong analog/mixed-signal background and at least 10 years of experience in analog/mixed-signal IP design, integration, and validation for SoC applications, or a Master’s degree with at least 7.5 years of such experience.
Strong understanding of SoC architecture, digital-analog interfaces, and system-level integration challenges.
Proven expertise in PLLs, high-speed SERDES, PVT sensors, IOs, and other analog building blocks.
Familiarity with industry-standard EDA tools for design, simulation, and verification.
Understanding of device physics and basic ESD/latch-up concepts.
Strong written and oral communication, problem-solving, and leadership skills.
Ability to work in a team environment and quickly ramp up on new projects.
Nice to have
Experience with PCIe, SAS, SATA, and Ethernet protocols.
Experience with chiplet technologies.
Culture & Benefits
Values-based environment focused on trust, empowerment, respect, diversity, communication, and employee development.
Health benefits begin on the first day.
Retirement savings plans and an employee stock purchase plan with a two-year look-back feature.
Total compensation includes base pay, restricted stock units, and quarterly bonus payments.
Leadership development programs and opportunities for career growth.
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