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7 часов назад

Principal Engineer - Analog Design (IP Tech Lead)

75 000 - 232 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Principal Engineer - Analog Design (IP Tech Lead) (Mixed-Signal SoC IP): Leading the architecture, integration, licensing, and silicon validation of analog and mixed-signal IPs for advanced SoC projects with an accent on high-speed SERDES, PLLs, PVT sensors, and I/O interfaces. Focus on defining IP specifications, resolving cross-functional integration issues, and debugging silicon after fabrication.

Location: Chandler, Arizona, United States; onsite role with 0%–25% travel.

Annual base salary: $75,000–$232,000, plus restricted stock units and quarterly bonus payments.

Company

hirify.global develops semiconductor products and analog and mixed-signal technologies for SoC and wireline applications.

What you will do

  • Provide end-to-end technical leadership for mixed-signal IPs across advanced SoC projects.
  • Define and review IP interface specifications, integration guidelines, and verification plans.
  • Evaluate, select, license, and customize third-party and internally developed IPs with vendors.
  • Architect and drive the integration of SERDES, PLLs, PVT sensors, I/Os, and other analog IPs into SoC designs.
  • Review system-level clocking requirements and support electrical compliance.
  • Coordinate with design, verification, physical design, and test teams during integration, silicon validation, characterization, and debug.

Requirements

  • Bachelor’s degree in electrical engineering or a related field with at least 10 years of analog/mixed-signal IP experience, or a master’s degree with at least 7.5 years of relevant experience.
  • Strong understanding of SoC architecture, digital-analog interfaces, and system-level integration.
  • Expertise in PLLs, high-speed SERDES, PVT sensors, I/Os, and other analog building blocks.
  • Experience with industry-standard EDA tools for design, simulation, and verification.
  • Understanding of device physics and basic ESD/latch-up concepts.
  • Strong communication, problem-solving, leadership, and teamwork skills.

Nice to have

  • Experience with PCIe, SAS, SATA, or Ethernet protocols.
  • Experience with chiplet technologies.

Culture & Benefits

  • Health benefits begin on the first day of employment.
  • Retirement savings plans and an employee stock purchase plan with a two-year lookback feature.
  • Restricted stock units and quarterly bonus payments are part of the total compensation package.
  • Employee development and leadership programs are available.

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