ASIC Design Verification Engineer (Ethernet/PCIe)

Location: Onsite opportunities in Irvine, California; San Jose, California; or Richmond, British Columbia, Canada

Annual base salary: USD 121,900–195,000

Company

hirify.global develops high-performance semiconductor and networking technologies for AI infrastructure, cloud operators, and data centers.

What you will do

• Develop next-generation high-throughput Ethernet devices focused on performance and power efficiency.
• Work on PCIe and other host-interface designs across the ASIC front-end development process.
• Define architecture, implement RTL, and perform simulation and verification.
• Support synthesis, timing closure, and silicon validation.
• Collaborate with worldwide design and architecture teams on a new device and product line.
• Contribute technical leadership as the product evolves across multiple generations.

Requirements

• BSEE with 8+ years of industry experience, or MSEE with 6+ years of industry experience.
• Experience in high-speed communication chip architecture and RTL design.
• Hands-on experience with the ASIC design process, including architecture definition, RTL coding, simulation, verification, synthesis, timing closure, and silicon validation.
• Strong knowledge of Ethernet controllers or PCIe is highly desired.
• Scripting experience with Python or Perl, along with strong communication and documentation skills.
• Self-starter and effective team player.

Culture & Benefits

• Work with a highly skilled, collaborative worldwide design and architecture organization.
• Medical, dental, and vision plans.
• 401(k) participation with company matching and an Employee Stock Purchase Program.
• Discretionary annual bonus and new-hire and annual equity awards.
• Paid holidays, sick leave, vacation, family leave, and other applicable leaves of absence.