Engineer I-Design (RTL/ASIC)

Location: Allentown, Pennsylvania, United States; full-time onsite role. Applicants must provide proof of U.S. citizenship, permanent U.S. residency, or protected-individual status under 8 USC 1324b(a)(3).

Company

hirify.global develops semiconductor products and solutions used in imaging, networking, system connectivity, computing, and data storage.

What you will do

• Design, simulate, and verify RTL-based blocks for SoC devices.
• Create detailed module designs, performance analyses, and design specifications.
• Implement RTL and support synthesis, formal verification, simulation, and pre-layout/post-layout timing verification.
• Develop high-speed design techniques that improve data and command-processing bandwidth, reduce latency, and increase reliability.
• Support design porting to test chips and emulation platforms.

Requirements

• 0–2.5 years of experience in RTL design for ASIC implementation.
• Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
• Practical experience with RTL design, synthesis, formal verification, RTL/gate-level simulation, clock-domain analysis, and static timing analysis.
• Proficiency in SystemVerilog, Verilog simulation tools, TCL, Perl or Python, and Linux.
• Ability to design complex state machines and datapath logic, understand industry standards, and write detailed design specifications.
• Eligibility for access to U.S.-controlled technology requires U.S. citizenship, permanent U.S. residency, or protected-individual status.

Nice to have

• Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
• FPGA and ASIC system-on-chip design experience.
• Laboratory experience with system-level validation.

Culture & Benefits

• Employee development and career-growth programs.
• Values-based decision-making and a collaborative team environment.
• Focus on innovation, diversity, communication, and community.
• Employment within a large global semiconductor organization.