Senior Design Verification Engineer (Emulation)

Location: Hybrid in Sunnyvale, California, United States; work from an HPE office an average of 2 days per week.

Base salary: USD 153,500–310,500 annually in California, United States; variable incentives may also be offered.

Company

hirify.global is a global edge-to-cloud company helping organizations connect, protect, analyze, and act on data and applications.

What you will do

• Develop and execute IP-level and system-level verification plans for complex digital designs.
• Build, maintain, and enhance UVM/SystemVerilog testbench environments with scoreboards, monitors, drivers, and coverage models.
• Develop and run directed and constrained-random tests to achieve functional and code coverage goals.
• Configure and operate Cadence Palladium, Synopsys ZeBu, or Mentor Veloce emulation platforms for system-level verification and performance validation.
• Collaborate with design, architecture, validation, software, and firmware teams to define strategies, review specifications, identify corner cases, and support early bring-up.
• Debug hardware issues, develop SVA assertions, drive coverage closure, produce sign-off reports, and improve verification flows and infrastructure.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science.
• 5–8 years of professional experience in design verification of digital or mixed-signal designs.
• Strong proficiency in SystemVerilog and UVM methodology.
• Hands-on experience with emulation-based verification platforms, such as Cadence Palladium, Synopsys ZeBu, or Mentor Veloce.
• Understanding of digital design concepts, including RTL design, synthesis constraints, and timing.
• Experience with constrained-random verification, functional coverage, and code coverage-driven methodologies.
• Experience debugging complex hardware designs with simulation and emulation tools.
• Familiarity with Python, Perl, or TCL for automation and flow development.
• Strong analytical and problem-solving skills with excellent attention to detail.

Nice to have

• Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience with Ethernet, TCP/IP, PCIe, CXL, AXI, AHB, APB, AMBA, I2C, SPI, or UART protocols.
• Experience with formal verification tools and techniques such as JasperGold or VC Formal.
• Familiarity with FPGA prototyping platforms and flows, power-aware verification using UPF/CPF, and SoC-level or full-chip integration verification.
• Knowledge of ARM, RISC-V, or x86 processor architectures and software-driven verification techniques.
• Experience with continuous integration and regression management frameworks.
• Familiarity with AI/ML applications and architectures, including generative AI skills, marketplaces, or agentic applications.
• Published work or patents in design verification.

Culture & Benefits

• Hybrid work model with flexibility to manage work and personal needs.
• Health and wellbeing benefits supporting physical, financial, and emotional wellbeing.
• Personal and professional development programs supporting career growth and specialization.
• Inclusive workplace that values varied backgrounds and individual uniqueness.