Senior Design Verification Engineer (Emulation)

Location: Hybrid, with an average requirement of 2 days per week from an HPE office. The listed salary range applies to the United States of America, including California.

Salary: USD 153,500–310,500 annual base salary in California, with potential variable incentives.

Company

hirify.global is a global edge-to-cloud technology company developing solutions that connect, protect, analyze, and manage data and applications.

What you will do

• Develop and execute IP-level and system-level verification plans for complex digital and mixed-signal designs.
• Build and maintain UVM/SystemVerilog testbenches, including scoreboards, monitors, drivers, coverage models, and assertions.
• Develop directed and constrained-random tests and drive functional and code coverage closure.
• Configure and run designs on Cadence Palladium, Synopsys ZeBu, or Mentor Veloce emulation platforms for system-level verification and performance validation.
• Collaborate with design, architecture, validation, software, and firmware teams to review specifications, identify corner cases, and support early bring-up.
• Debug hardware issues using waveform, log, simulation, and emulation-platform analysis, and prepare verification sign-off reports.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 5–8 years of professional experience in design verification of digital or mixed-signal designs.
• Strong proficiency in SystemVerilog and UVM, with experience in constrained-random verification and coverage-driven methodologies.
• Hands-on experience with emulation-based verification platforms such as Cadence Palladium, Synopsys ZeBu, or Mentor Veloce.
• Understanding of RTL design, synthesis constraints, timing, and complex hardware debugging.
• Proficiency in Python, Perl, or TCL for automation and flow development.

Nice to have

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience with Ethernet, TCP/IP, PCIe, CXL, AXI, AHB, APB, AMBA, I2C, SPI, or UART protocols.
• Experience with formal verification, FPGA prototyping, power-aware verification, SoC-level verification, or processor architectures such as ARM, RISC-V, and x86.
• Experience with continuous integration and regression management frameworks.
• Knowledge of AI/ML applications and architectures, including generative AI and agentic applications.

Culture & Benefits

• Hybrid work arrangement with regular access to an HPE office.
• Health, financial, and emotional wellbeing benefits for employees and their loved ones.
• Professional development programs supporting expert and cross-functional career growth.
• Inclusive workplace focused on varied backgrounds, flexibility, collaboration, and innovation.