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6 дней назад

FPGA Design Engineer

110 000 - 170 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
FPGA Design Engineer (Verilog/SystemVerilog, Ethernet): Developing and verifying high-performance control-path FPGAs for next-generation data center and Ethernet networking platforms with an accent on RTL design, FPGA implementation, timing closure, and system bring-up. Focus on integrating networking interfaces, debugging hardware in the lab, automating EDA workflows with Python and Tcl, and solving complex resource, clock-domain, and verification challenges.

Location: Roseville, California, USA; local to the Bay Area required

Base pay: $110,000–$170,000 per year, plus potential discretionary bonuses and equity.

Company

hirify.global develops client-to-cloud networking solutions for data centers, campuses, routing environments, and AI clusters.

What you will do

  • Develop, integrate, simulate, and verify Verilog and SystemVerilog RTL, including custom testbenches.
  • Execute FPGA synthesis, place and route, timing closure, and in-system hardware debugging.
  • Drive system-level bring-up and debugging of next-generation network switch platforms with hardware and software teams.
  • Review RTL code, PCB schematics, and board designs with cross-functional engineering teams.
  • Develop Python, Tcl, AI, or shell scripts to automate FPGA design workflows and data processing.
  • Support FPGA development from architectural requirements through production deployment.

Requirements

  • 5+ years of hands-on experience with Verilog/SystemVerilog RTL design.
  • Background in control-path design and on-chip bus interfaces such as I2C, SPI, MDIO, PCIe, or AXI.
  • Must be local to the Bay Area and work in the Roseville, California area.
  • Ability to collaborate across hardware, software, manufacturing, and system engineering functions.
  • Experience interpreting board schematics and supporting FPGA verification, bring-up, and debugging.

Nice to have

  • Ethernet data-path architecture and design experience.
  • Streaming bus interfaces such as AXI-Stream.
  • FPGA resource management and timing closure experience.
  • Python, Tcl, or scripting experience for EDA tool automation.
  • Lab validation experience with logic analyzers, oscilloscopes, and vendor-specific debug tools.

Culture & Benefits

  • Work with cross-functional hardware, software, and manufacturing engineering teams.
  • Build networking products for enterprise campuses, hyperscale data centers, and AI clusters.
  • US-based employees receive medical, dental, vision, wellbeing, tax savings, and income protection benefits.
  • Potential eligibility for discretionary bonuses and equity.

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