Senior Design Verification Engineer

TL;DR

Senior Design Verification Engineer: end-to-end verification of critical chassis and interconnect IP blocks with an accent on testbench architecture, test plan and coverage closure, and unified simulation + formal bug hunting. Focus on driving functional signoffs and achieving performance/power metrics while mentoring verification engineers and leveraging AI-assisted workflows.

Location: US, California, Santa Clara

Salary: $164,470.00-311,890.00 USD (annual)

Company

hirify.global builds scalable engineering solutions across IP, custom ASIC, and foundry enablement.

What you will do

• Own verification planning and execution for key IP features across IP and subsystem integration points.
• Build scalable verification environments and targeted test plans using reusable testbenches, checkers, VIPs, and behavioral models.
• Collaborate with architecture, design, and software teams from specification through bringup; contribute across boundaries to unblock progress.
• Drive ownership of multiple critical blocks and verification components, including functional signoffs and achievement of performance and power metrics.
• Converge simulation and formal verification into unified bug hunting and coverage closure strategies; evaluate and adopt emerging methodologies (including ML-driven verification flows).
• Mentor and develop verification engineers; establish verification best practices and improve team execution quality.

Requirements

• 10+ years of experience in design verification (DV), including IP DV and subsystem/SoC-level verification.
• Experience verifying interconnects, caches, and memory subsystems, including AMBA (CHI/ACE/AXI), PCIe, UCIe, and CXL; cache coherency and memory consistency models.
• Experience with global function verification (debug, trace, clock/power management, RAS, QoS, security).
• Proficiency with simulation and formal verification methodologies and tools (UVM, SVA, ABV, co-simulation; UVM/SystemVerilog; industry-standard EDA tools), including low-power verification techniques.
• Hands-on coding experience across SystemVerilog/UVM, C/C++, Python, and build systems.
• Experience working with RTL, physical design, and CAD tool flows; ability to contribute outside core DV responsibilities as needed.

Culture & Benefits

• Hybrid work model: split time between on-site at the assigned hirify.global site and off-site.
• Total compensation includes competitive pay, stock bonuses, and benefits such as health, retirement, and vacation.
• AI-assisted workflows are part of everyday development.
• Emphasis on consistent execution against schedule and quality goals.

Hiring process

• Application review based on minimum and preferred qualifications.
• Recruiter shares location-specific compensation details during the hiring process.