Digital Design Engineer (Ethernet)

Location: On-site in the Bay Area, Vancouver, or Toronto; Monday through Friday

Company

Develop chiplet technologies for high-volume, high-performance systems with a focus on power, area, manufacturability, and design flexibility.

What you will do

• Design, develop, and integrate Ethernet PCS/PMA IPs for 100G, 200G, 400G, and 800G data rates.
• Define micro-architectures and implement digital designs using SystemVerilog and assertion coding.
• Optimize designs for power, area, and performance, including synthesis and frontend netlist optimization.
• Ensure compliance with IEEE 802.3 Ethernet standards, including Auto-Negotiation and Link Training.
• Collaborate with verification and physical design engineers on IP verification and physical implementation.
• Maintain RTL, documentation, SDC constraints, power-intent definitions, and LINT/CDC rule files and waivers.

Requirements

• Bachelor’s, Master’s, or Ph.D. in Electrical Engineering or a related field, or equivalent experience.
• 5+ years of high-speed digital design experience, preferably with retimer, gearbox, Ethernet PMA, or PCS logic.
• Strong expertise in RTL and assertion coding with SystemVerilog.
• Experience taking RTL through synthesis and producing a PPA-optimized frontend netlist.
• Knowledge of IEEE 802.3 clauses for 100G, 200G, 400G, and 800G Ethernet, Auto-Negotiation, and Link Training.
• Willingness to work on-site Monday through Friday in the Bay Area, Vancouver, or Toronto.

Nice to have

• Experience integrating third-party mixed-signal IPs.
• Knowledge of DRAM controllers, PHYs, and HBM memory.
• Experience in a startup-like environment.

Culture & Benefits

• Fast-paced early-stage startup environment.
• Cross-functional collaboration with engineering experts.
• Focus on innovation, design automation, and quality improvement.
• Fun work environment with excellent benefits.