Principal NoC IP Micro-Architect (FPGA)

Location: San Jose, California, United States

Salary: $209,500–$299,200 USD annually for the Bay Area, California

Company

hirify.global is an independent FPGA solutions provider developing programmable technologies for AI, cloud, networking, and edge markets.

What you will do

• Define the architecture and microarchitecture of scalable Network-on-Chip IP and FPGA subsystems.
• Develop RTL logic, simulations, prototypes, and system requirements for full-chip integration.
• Deliver software models supporting device-level bring-up, user-visible functionality, timing, and power analysis.
• Optimize RTL implementations for power, performance, area, scalability, and reliability in partnership with physical design.
• Collaborate with architecture, verification, software, physical design, and product teams to resolve design challenges.
• Provide technical leadership for the NoC team and mentor developing technical members.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field, with 15+ years of related experience.
• 10+ years of experience with SystemVerilog, VCS or Synopsys simulators, lint, and synthesis.
• 10+ years of experience developing Network-on-Chip IP.
• 10+ years of programming experience with C, C++, Perl, Python, TCL, and Unix shell scripting.
• Experience with RTL validation, FPGA design, timing constraints, CDC, RDC, DFT, and advanced EDA tools.
• Applicants must be eligible for any required U.S. export authorizations.

Nice to have

• 10+ years of experience in FPGA design and programming.
• 10+ years of experience in RTL validation.
• 5+ years of using AI in development processes to improve efficiency.

Culture & Benefits

• Regular, full-time employment.
• Incentive opportunities based on individual and company performance.
• Cross-functional collaboration across architecture, design, verification, software, physical design, and product teams.