Digital Verification Intern (SystemVerilog/UVM)

Location: Barcelona, Spain

Company

hirify.global develops integrated power semiconductors and system-level power delivery architectures for the semiconductor industry.

What you will do

• Assist with creating digital verification environments using UVM and SystemVerilog.
• Write digital and mixed-signal testcases, assertions, and checkers.
• Analyze and debug test results, code coverage, and functional coverage.
• Support verification IP, standard tests, environments, and checkers.
• Generate test plans from design requirements and product datasheets.
• Support system-level and behavioral model development, automation, scripting, and gate-level verification.

Requirements

• Bachelor’s or master’s degree in Electrical Engineering with coursework in digital design or VLSI.
• Basic knowledge of ASIC development processes and digital design techniques.
• Knowledge of SystemVerilog, UVM, and behavioral or RTL coding.
• Ability to follow design specifications and procedures and complete tasks aligned with project milestones.
• Good written and verbal communication skills, teamwork, and collaboration.

Nice to have

• Knowledge of SCAN and other DFT techniques.
• Experience with power management applications.
• Knowledge of I2C, I3C, SPI, USB, or PMBUS.
• Scripting and automation experience with TCL, Python, or C/C++.

Culture & Benefits

• Full-time internship within a semiconductor technology company.
• Work on leading-edge digital and mixed-signal IC technologies.
• Collaborate with senior digital design, digital verification, and analog design engineers.
• Environment focused on creativity, sustainability, and product innovation.