Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Зарплата и рынок
$147к-279к/год
$180к$200кмедиана$230к
По похожим ролям (48) ~ $200к/год
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Крутая вакансия
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Чёткая зона ответственности, влияние на технические решения и работа с HPC и AI-инфраструктурой делают роль сильной возможностью, хотя порог в 10+ лет опыта и привязка к одному из трёх офисов сужают выбор.
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Влияние на решенияАктуальные технологииПерспективная областьТри офиса
Оценка от Hirify AI
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Senior ASIC Design Verification Engineer - Slingshot (HPC/AI): Developing pre-silicon verification for switch and NIC ASICs used in high-performance computing and AI interconnects with an accent on SystemVerilog, UVM, coverage closure, and verification methodology. Focus on building block and integration-level testbenches, triaging regression failures, driving bug closure, and applying AI-assisted workflows to complex verification problems.
Location: Hybrid, with an average of 2 days per week from an HPE office in Chippewa Falls, Wisconsin; Fort Collins, Colorado; or Bloomington, Minnesota, United States.
Base salary: USD 147,000–279,000 annually in Colorado; USD 140,000–321,000 annually in Minnesota and Wisconsin. Variable incentives may also be offered.
Company
hirify.global is a global edge-to-cloud technology company developing infrastructure and solutions for data, applications, high-performance computing, and AI systems.
What you will do
Own significant pre-silicon design verification scope for future-generation Slingshot switch and NIC ASICs.
Define and apply verification methodology, develop test plans and SystemVerilog/UVM testbench components, and build bus functional models.
Implement block- and integration-level scoreboards and checkers, analyze functional coverage, and support milestone decisions and sign-off reviews.
Triage regression failures, identify logic bugs, and drive bug closure.
Apply scripting, automation, and AI-assisted or agentic tools to improve verification speed and quality.
Mentor less experienced engineers, influence technical direction, and contribute to future technical-leader selection and VLSI innovation.
Requirements
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
10+ years of experience in VLSI design, verification, or implementation.
Expert-level knowledge of SystemVerilog and OVM or UVM methodologies.
Expert-level knowledge of programming and scripting languages, hardware description languages, EDA, and/or FPGA tools.
Expert-level analytical and problem-solving skills.
Ability to excel in a distributed team environment.
Executive-level written and verbal communication skills and mastery in English.
Nice to have
Experience verifying high-speed networking, switching, or NIC ASICs.
Experience with agentic AI coding tools and workflows applied to verification.
Experience with Python, Perl, Tcl, or another scripting language in Linux development environments.
Experience working as part of a geographically distributed team.
Culture & Benefits
Hybrid work with regular access to an HPE office.
Health and wellbeing benefits for employees and their families.
Personal and professional development programs supporting career growth and technical expertise.
Inclusive workplace committed to valuing varied backgrounds and individual uniqueness.
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