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6 дней назад

Senior Physical Design Engineer (Neuromorphic Computing)

164 470 - 269 100$
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify RU Global, списка компаний с восточно-европейскими корнями
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Описание вакансии

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TL;DR
Senior Physical Design Engineer (Neuromorphic Computing): Engineering chiplet and advanced-packaging physical integration solutions for next-generation neuromorphic AI silicon with an accent on full-chip floorplanning, timing closure, and power-performance-area optimization. Focus on solving EM/IR, LVS, DRC, and timing violations, building physical-design tool flows, and applying AI-driven automation and debug.

Location: Hybrid work model in the United States, with on-site work at an assigned hirify.global site. Primary location: Hillsboro, Oregon; additional locations: Folsom and Santa Clara, California.

Annual salary: $164,470–$269,100 USD.

Company

hirify.global designs and manufactures silicon products and develops neuromorphic computing technologies for physical AI systems.

What you will do

  • Engineer physical integration solutions across chiplet and advanced packaging technologies.
  • Architect full-chip floorplans and support partition-level floorplans, including macro and pin placement and keep-outs.
  • Define timing constraints with RTL designers and run synthesis and place-and-route trials.
  • Drive block- and chip-level closure by resolving timing, EM/IR, LVS, and DRC violations.
  • Run back-annotated VCS and SDF simulations and provide design feedback to meet power and performance targets.
  • Develop scripts and tool flows for low-power, high-performance physical design.

Requirements

  • Bachelor’s degree with 6+ years or master’s degree with 4+ years of hands-on physical design experience and multiple silicon tape-outs.
  • 6+ years of experience with floorplanning, timing and power constraints, synthesis, and place and route.
  • 6+ years of experience with scripting languages such as Perl, TCL, or Python.
  • 4+ years of experience debugging FEV and RV reports and planning ECOs.
  • 2+ years of experience with chiplet integration or advanced packaging.
  • 1+ year of experience using AI tools for tool-flow setup, debugging, and productivity improvement.

Nice to have

  • Static timing experience with interfaces such as SerDes and UCIe.
  • Experience with Cadence Virtuoso and Synopsys tools, including Fusion Compiler, PrimeTime, StarRC, SiliconSmart, and VCS.
  • EDA/CAD software development experience with Java or C++.
  • Experience with asynchronous architectures and circuits.

Culture & Benefits

  • Hybrid work model combining on-site and off-site work.
  • Competitive compensation with stock bonuses.
  • Health, retirement, and vacation benefits.
  • Work on neuromorphic computing research and product development with a global ecosystem of research groups.

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