SOC Timing Engineer

Location: Penang 15, Penang, Malaysia

Company

hirify.global develops semiconductor and programmable logic technologies.

What you will do

• Perform static timing analysis for FPGA, SoC, and subsystem designs.
• Drive timing closure and final timing signoff.
• Provide and derive interface timing constraints for design partitions.
• Analyze timing convergence with design and architecture teams.
• Collaborate with physical design teams on timing closure.

Requirements

• 3+ years of experience in physical design and timing closure or signoff.
• Experience with static timing analysis and industry-standard EDA tools, including PrimeTime and PTPX.
• Good understanding of timing constraints, clocking, and PVT analysis.
• Tapeout experience with 10 nm or smaller technology nodes.
• BE, MS, or PhD in Electronics or Electrical Engineering.
• Strong communication, problem-solving, and analytical skills.

Culture & Benefits

• Regular full-time employment.
• Shift 1 schedule aligned with Malaysia.