Lead STA Engineer (ASIC)

Location: San Jose, CA; Pittsburgh, PA; or Austin, TX

Salary: $200,000–$250,000 per year, plus equity and benefits.

Company

hirify.global develops energy-efficient, programmable general-purpose processors for continuous AI/ML computing in IoT devices and edge applications.

What you will do

• Develop timing flows and methodology from scratch for advanced FinFET and multi-patterning process technologies using Cadence Tempus or Synopsys PrimeTime.
• Own timing convergence and sign-off for IP, subsystem, and SoC blocks across multiple tape-outs.
• Define timing margins, PVTRC corners, extraction methodology, and synthesis/place-and-route sign-off correlation.
• Develop slew-rate, glitch-noise, and custom timing checks for the proprietary ultra-low-power architecture.
• Collaborate with RTL, DFT, IP vendors, and post-silicon bring-up teams to define constraints and ensure timing correlation.
• Coordinate third-party timing resources and improve flow consistency and efficiency across product lanes.

Requirements

• Master's degree in Electrical Engineering with 5+ years of industry experience, or PhD in Electrical Engineering with 3+ years of industry experience.
• Proven IP, subsystem, or SoC STA sign-off experience across multiple tape-outs using 12nm or smaller process technologies.
• Hands-on experience with Cadence, Synopsys, or Mentor EDA tools for STA and simulation, including hierarchical design and abstraction techniques.
• Expert knowledge of static timing analysis, SDC constraints and exceptions, timing corners, voltage definitions, and timing margining.
• Experience with high-frequency, low-power designs and timing-related power tradeoffs.
• Strong scripting skills in TCL, shell, and Python.

Nice to have

• Knowledge of computer architecture, physical design, ASIC implementation, circuit design, device physics, deep-submicron, or SOI technology.
• Experience with full-chip sign-off budgeting, physical design flows, and CAD infrastructure for physical design engineers.
• Experience integrating analog or mixed-signal macros into top-level designs.

Culture & Benefits

• Opportunity to join an early-stage hardware engineering organization and influence products from initial development through volume production.
• Cross-functional collaboration within an interdisciplinary hardware engineering team.
• Competitive compensation with meaningful equity.
• 401(k) match, company-paid benefits, paid parental leave, and flexibility.
• Support for personal and professional development.