Senior Physical Design Engineer

TL;DR

Senior Physical Design Engineer (RTL-to-GDS): Execute end-to-end physical design for custom IP and SoC, from RTL implementation through GDS, with an accent on timing closure, power/noise integrity, and manufacturability. Focus on building reliable flows using EDA tools and scripting to optimize for power, frequency, and area under advanced process-node constraints.

Location: Malaysia, Penang

Company

hirify.global builds scalable engineering solutions across product enablement, custom ASIC, and foundry enablement.

What you will do

• Deliver RTL-to-GDS implementation for custom IP and SoC, including synthesis, place-and-route, clock tree synthesis, and floor planning.
• Run static timing analysis plus power, noise, and reliability assessments to meet stringent design specifications.
• Perform verification and signoff, including formal equivalence verification, layout verification, and static/dynamic power integrity checks.
• Identify and resolve design violations while optimizing power, frequency, and area.
• Develop and refine physical design methodologies using EDA tools to improve automation and workflow efficiency.
• Use scripting (Perl/TCL/Python/Shell) to automate repetitive tasks and debug design anomalies; collaborate with architecture and logic designers.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
• 6+ years of physical/structural design experience with a Bachelor’s degree (or 4+ years with a Master’s, or 2+ years with a PhD).
• Proficiency in RTL-to-GDS tools and methodologies (synthesis, place-and-route, clock tree synthesis, floor planning).
• Deep expertise in static timing analysis, including SDC development, timing budgeting, and timing signoff (e.g., Primetime).
• Strong scripting skills in Perl, TCL, Python, or Shell to automate workflows and debug issues.
• Experience with EDA tools/flows including low-power design and multi-power domain analysis; multiple tape-outs for deep sub-micron process nodes.

Nice to have

• Advanced experience in I/O and IP timing budget development.
• Familiarity with Verilog or VHDL.
• Track record mentoring and developing junior team members.
• Strong organizational and multitasking skills for high-quality delivery under tight deadlines.

Culture & Benefits

• Hybrid work model: split time between on-site work at the assigned hirify.global site and off-site work.
• Collaborative engineering environment across architecture and logic design teams.
• Focus on continuous improvement of physical design processes for advanced process nodes.
• Opportunity to contribute to high-performance computing and next-generation architectures.

Hiring process

• Application review for qualified candidates.
• Employment consideration without regard to protected characteristics.