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5 дней назад

SOC Physical Design Static Timing Analysis Engineer

164 470 - 311 890$
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify RU Global, списка компаний с восточно-европейскими корнями
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Описание вакансии

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TL;DR

SOC Physical Design Static Timing Analysis Engineer: Performing SOC-level timing analysis and optimization for cutting-edge chip designs with an accent on timing closure, clock network development, and constraint verification. Focus on balancing power, performance, and area (PPA) while collaborating with cross-functional architecture and design teams to ensure high-quality silicon execution.

Location: Hybrid role based in Phoenix, AZ or Santa Clara, CA (US)

Salary: $164,470–$311,890 USD

Company

A global leader in computing innovation, semiconductor manufacturing, and technology solutions.

What you will do

  • Perform SOC-level timing analysis and optimization to meet functional and performance requirements.
  • Generate and verify timing constraints while resolving violations at the chip or block level.
  • Develop optimized clock networks to enhance functionality, power efficiency, and performance.
  • Define methodologies for high-quality timing models and efficient physical design execution.
  • Establish PVT conditions for timing analysis aligned with product plans and binning strategies.
  • Collaborate with architecture, clocking, DFT, and logic design teams to validate clock network performance.

Requirements

  • Bachelor's degree with 8+ years, Master's with 6+ years, or PhD with 4+ years in Electrical/Computer Engineering or related field.
  • 7+ years of technical proficiency in SOC-level static timing analysis, clock network design, and timing closure.
  • 3+ years of experience in timing constraint adaptation and physical design optimization.
  • Strong expertise in industry-standard tools for timing analysis, extraction, and physical design.
  • Familiarity with TCL scripting and timing budgeting processes.
  • Must be eligible to work in the United States.

Nice to have

  • Knowledge of DFT architecture.
  • Experience with SoC clocking methodologies and disciplined digital design execution.
  • Strong communication skills for articulating complex technical concepts.

Culture & Benefits

  • Competitive total compensation package including base pay and stock bonuses.
  • Comprehensive health, retirement, and vacation benefit programs.
  • Hybrid work model allowing flexibility between on-site and off-site work.
  • Opportunity to work on complex, high-impact designs at a global scale.

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