Signal Integrity/ Power Integrity Engineer

Location: Haifa, Israel; additional locations in Jerusalem and Tel Aviv, Israel. Shift 1 (Israel).

Company

hirify.global develops programmable FPGA, CPLD, and IP solutions for high-speed connectivity, AI acceleration, and next-generation data infrastructure.

What you will do

• Support SERDES IP system simulations, including reference channel definition and parameter extraction.
• Review and validate silicon IP parameters together with package and PCB designs against interface specifications.
• Participate in package and PCB schematic and layout reviews, analyze simulation results, and help debug failures.
• Apply signal and power integrity concepts to mixed-signal, channel, SIPI circuit, channel, and IO simulations.
• Support optimization of package and PCB designs to meet power, performance, and signal integrity requirements.
• Collaborate with internal teams on IP, package, and PCB integration and design delivery.

Requirements

• B.Sc. or M.Sc. in Electrical Engineering from a recognized university.
• Strong background in electromagnetic and wave theory.
• Junior-level profile with relevant university project experience and motivation to develop hands-on design skills.
• Experience with ASIC package design, including pinout optimization, stack-ups, and high-speed routing.
• Knowledge of silicon floor planning, signal integrity, power integrity, high-speed signal design, and power distribution networks.
• Hands-on experience with oscilloscopes and TDR/VNA analyzers; an academic grades sheet must be included with the application.

Culture & Benefits

• Work alongside experienced engineers in a multidisciplinary SERDES Analog team.
• Regular full-time employment position.
• Work on advanced mixed-signal and high-speed connectivity technologies.