4 часа назад
PCIe Post-Silicon Validation Engineer
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
PCIe Post-Silicon Validation Engineer (PCIe): Performing hands-on post-silicon validation and debugging PCIe links across silicon, firmware, software, and signal-integrity boundaries with an accent on link training, LTSSM, equalization, recovery, and link stability. Focus on analyzing protocol traces and lab measurements, driving failures to root cause, and building automation for stress, interoperability, and regression testing.
Location: Tel Aviv-Yafo, Tel Aviv District, Israel
Company
develops semiconductor-based connectivity solutions and software for rack-scale AI infrastructure, integrating technologies such as CXL, Ethernet, NVLink, PCIe, and UALink.
What you will do
- Perform hands-on PCIe post-silicon validation across generations, platforms, configurations, and operating conditions.
- Debug link training, LTSSM, equalization, recovery, resets, stability, and other PCIe link issues.
- Analyze state-machine and protocol traces, registers, logs, eye diagrams, and signal-integrity measurements.
- Drive complex failures from initial reproduction through root-cause analysis and final resolution.
- Develop validation plans, stress tests, corner-case scenarios, interoperability tests, and regression automation.
- Collaborate with silicon, design, architecture, firmware, software, and signal-integrity engineers.
Requirements
- BS or MS degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
- At least 5 years of experience in silicon validation, post-silicon debugging, or high-speed interface development.
- Strong hands-on knowledge of PCIe architecture and protocol.
- Experience with PCIe analyzers, state traces, registers, logs, eye diagrams, and signal-integrity measurements.
- Good scripting or programming skills, preferably Python, along with Linux knowledge and PCIe debug tools.
- Ability to independently solve problems and collaborate across hardware, firmware, and software boundaries.
Nice to have
- Experience with PCIe Gen4, Gen5, Gen6, or Gen7.
- Hands-on experience with PCIe PHY, SerDes, equalization, lane margining, or signal integrity.
- Experience with PCIe compliance, interoperability testing, PCIe switches, networking platforms, or accelerator platforms.
- Experience debugging intermittent, marginal, thermal-sensitive, or corner-case PCIe failures.
- Practical use of AI/ML tools for engineering debugging and automation.
Culture & Benefits
- Work with cross-functional engineering teams spanning design, architecture, firmware, software, and silicon development.
- Inclusive environment that encourages applications from people with diverse backgrounds and experiences.
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