14 ΡΠ°ΡΠΎΠ² Π½Π°Π·Π°Π΄
Expert IC Package Design Lead (Semiconductor)
ΠΡΡΡ & Π‘ΠΎΠΏΡΠΎΠ²ΠΎΠ΄
ΠΠ»Ρ ΠΌΡΡΡΠ° Ρ ΡΡΠΎΠΉ Π²Π°ΠΊΠ°Π½ΡΠΈΠ΅ΠΉ Π½ΡΠΆΠ΅Π½ Plus
ΠΠΏΠΈΡΠ°Π½ΠΈΠ΅ Π²Π°ΠΊΠ°Π½ΡΠΈΠΈ
Π’Π΅ΠΊΡΡ:
TL;DR
Expert IC Package Design Lead (Semiconductor): Owning the architecture, design, qualification, and production release of advanced IC packages for high-performance connectivity silicon with an accent on signal integrity, power integrity, thermal performance, and manufacturability. Focus on designing complex BGA, FCBGA, FCCSP, interposer, and chiplet-based packages, driving OSAT collaboration, and resolving reliability and production-ramp challenges.
Location: Israel
Company
develops rack-scale AI infrastructure and semiconductor-based connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, UALink, and software technologies.
What you will do
- Own IC package design from architecture and feasibility through detailed design, qualification, tape-out, and high-volume manufacturing.
- Define package architectures and technology selections, including organic substrates, advanced laminates, interposers, and 2.5D/3D chiplet packaging.
- Lead package-level signal integrity, power integrity, thermal, mechanical, and cost trade-offs for high-speed, high-power devices.
- Drive package layout, substrate routing, bump and ball maps, stack-ups, material selection, and mechanical constraints.
- Collaborate with silicon, SerDes, system, SI/PI, reliability, manufacturing, OSAT, and substrate partners.
- Lead risk assessment, failure analysis, corrective actions, NPI, qualification, vendor audits, and product sustainment.
Requirements
- 10+ years of hands-on IC package design experience for high-performance semiconductor products, with ownership from concept through tape-out.
- Expert proficiency with Cadence APD, SiP, or equivalent IC package design tools.
- Experience designing complex BGA, FCBGA, and FCCSP packages.
- Strong expertise in package architecture and integration, including stack-ups, bump and ball maps, constraints, SMT integration, and package BOM ownership.
- Deep understanding of package-level signal, power, and thermal integrity, plus manufacturing and release processes including DRC, LVS, DFM, and OSAT engagement.
Nice to have
- Experience with AI, networking, PCIe, CXL, or other high-speed data center interfaces.
- Familiarity with JEDEC, IPC, thermal cycling, HTOL, and other package reliability and qualification standards.
- Experience with chiplet-based architectures and heterogeneous integration.
- Technical leadership or package ownership on high-volume products.
Culture & Benefits
- Opportunity to help establish a strategic R&D center in Israel.
- Work on connectivity silicon for large-scale AI and cloud environments.
- Inclusive environment encouraging applications from people with diverse backgrounds and experiences.
ΠΡΠ΄ΡΡΠ΅ ΠΎΡΡΠΎΡΠΎΠΆΠ½Ρ: Π΅ΡΠ»ΠΈ ΡΠ°Π±ΠΎΡΠΎΠ΄Π°ΡΠ΅Π»Ρ ΠΏΡΠΎΡΠΈΡ Π²ΠΎΠΉΡΠΈ Π² ΠΈΡ ΡΠΈΡΡΠ΅ΠΌΡ, ΠΈΡΠΏΠΎΠ»ΡΠ·ΡΡ iCloud/Google, ΠΏΡΠΈΡΠ»Π°ΡΡ ΠΊΠΎΠ΄/ΠΏΠ°ΡΠΎΠ»Ρ, Π·Π°ΠΏΡΡΡΠΈΡΡ ΠΊΠΎΠ΄/ΠΠ, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡΠ΅ ΡΡΠΎΠ³ΠΎ - ΡΡΠΎ ΠΌΠΎΡΠ΅Π½Π½ΠΈΠΊΠΈ. ΠΠ±ΡΠ·Π°ΡΠ΅Π»ΡΠ½ΠΎ ΠΆΠΌΠΈΡΠ΅ "ΠΠΎΠΆΠ°Π»ΠΎΠ²Π°ΡΡΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡΠΈΡΠ΅ Π² ΠΏΠΎΠ΄Π΄Π΅ΡΠΆΠΊΡ. ΠΠΎΠ΄ΡΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β
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