Principal Package Signal & Power Integrity

Location: San Jose, California, United States

Salary: $203,000–$230,000 USD per year

Company

hirify.global provides rack-scale AI infrastructure through purpose-built connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, UALink, and software technologies.

What you will do

• Architect, optimize, and sign off package signal and power integrity solutions for high-performance connectivity products.
• Lead SI and PI simulations for PCIe, CXL, Ethernet, 200G/400G+ SerDes, and die-to-die interconnects.
• Drive package electrical architecture across FCBGA, coreless, chiplet-based, 2.5D/3D, interposer, bridge-based, and heterogeneous multi-die packages.
• Coordinate silicon, package, PCB, validation, manufacturing, substrate, and OSAT stakeholders while balancing performance, cost, manufacturability, reliability, yield, and schedule.
• Establish simulation-to-measurement correlation using EM extraction, system models, VNA, TDR, and high-speed oscilloscope validation.
• Define SIPI modeling standards, routing guidelines, design rules, automation flows, and signoff methodologies while mentoring engineers.

Requirements

• 10+ years of experience in signal integrity, power integrity, package electrical design, or chip–package–board co-design for high-performance semiconductor products.
• Deep expertise in package SIPI modeling, analysis, optimization, and signoff for high-speed SerDes, PCIe, CXL, and Ethernet.
• Experience with PCIe 5.0/6.0, PAM4 SerDes, S-parameter extraction, package models, eye-diagram analysis, loss optimization, and crosstalk analysis.
• Hands-on experience with HFSS, SIwave, Q3D, 3D Layout, Keysight ADS, Cadence Sigrity, or equivalent tools.
• Expert knowledge of PDN design, including IR drop, AC impedance, target impedance, loop inductance, decoupling, transient response, and noise coupling.
• Experience correlating simulations with lab measurements and leading vendor engagements through production ramps.

Nice to have

• Experience influencing silicon floor planning, bump maps, SerDes and power-grid planning, package escape, and PCB breakout.
• Automation and scripting experience for SIPI modeling flows.
• Exposure to Allegro Package Designer and advanced package manufacturing and assembly processes.
• Experience with CPO and NPO optical package SIPI design and optical connectivity applications.

Culture & Benefits

• Work with cross-functional semiconductor, packaging, manufacturing, and ecosystem partner teams.
• Inclusive environment encouraging applications from people with diverse backgrounds and experiences.
• Role focused on creativity and innovation in AI infrastructure and connectivity technology.