Sr. Logic Design Engineer (RTL)

TL;DR

Sr. Logic Design Engineer (RTL): Developing logic design, RTL coding, and simulation for UCIE PHY IP for datacenter and server designs with an accent on power, performance, and area (PPA) optimization. Focus on designing data paths, power-management flows, and ensuring timing/power convergence for high-performance hardware.

Location: Hybrid; must be based in the US (Santa Clara, CA; Phoenix, AZ; or Hillsboro, OR)

Salary: $141,910 – $200,340 USD

Company

hirify.global is a global leader in semiconductor design and manufacturing, specializing in processors and hardware for data centers and consumer electronics.

What you will do

• Develop logic design, RTL coding, and simulation for IP blocks.
• Contribute to the definition of architecture and microarchitecture features of the assigned blocks.
• Perform quality checks from RTL to timing and power convergence.
• Optimize logic to meet power, performance, area, and timing goals.
• Review verification plans and resolve failing RTL tests to ensure feature correctness.

Requirements

• Bachelor's in Electrical/Computer Engineering (4+ years exp) or Master's (2+ years) or PhD (1+ year).
• Proficiency in RTL/Logic design using System Verilog.
• Experience with data path design, power-management flow, arbitration logic, CDC, and state machines.
• Experience with UPF and front-end design tools for Lint and Synthesis.
• Experience with hardware simulation tools such as VCS and Verdi.
• Must be eligible to work in the United States.

Nice to have

• Experience with UCIE PHY Design and Mixed-Signal environments.
• Knowledge of Cross Domain Crossing and Voltage Domain Crossings.

Culture & Benefits

• Competitive total compensation package including pay and stock bonuses.
• Comprehensive benefit programs including health, retirement, and vacation.
• Hybrid work model allowing employees to split time between on-site and off-site work.