Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
Пожаловаться
Зарплата и рынок
ЗП не указана
На похожих ролях по рынку
$143к$168кмедиана$200к
50 в выборке
На СНГ рынке: $1.9к/мес ($1.8к - $3к)
75
Хорошая вакансия
развернуть
Роль четко определена с ясным акцентом на технологии RISC-V, но отсутствие информации о зарплате затрудняет оценку общей привлекательности.
Кликните для подробной информации
Нет информации о зарплатеПродуктовая компанияЧеткие обязанностиТрендовый домен
Оценка от Hirify AI
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Подключить Plus
Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
System Validation Engineer to Staff Engineer (RISC-V): Developing, deploying, and supporting FPGA and emulation environments for RISC-V processor and SoC designs with an accent on system validation, verification methodology, and silicon bring-up. Focus on debugging complex hardware, software, and design failures, implementing test plans, and analyzing coverage and readiness for silicon and software bring-up.
Location: Hsinchu, Taiwan. Right to work in Taiwan and authorization to access export-controlled technology are required.
Company
hirify.global develops high-performance RISC-V compute platforms for artificial intelligence, machine learning, automotive, data center, mobile, and consumer applications.
What you will do
Develop, deploy, and support emulation and FPGA environments for RISC-V CoreIP and silicon designs.
Bring up silicon designs on FPGA platforms and identify root causes of design, test, and emulator-environment failures.
Collaborate with cross-functional teams to define and implement emulation strategies based on product goals.
Define emulation test strategies, test frameworks, and test plans.
Establish hardware and software readiness for silicon and software bring-up.
Debug complex emulation hardware, software, and silicon design issues.
Requirements
Solid understanding of processor and SoC architecture, or a strong desire and ability to learn it.
More than 3 years of direct system development, validation, and debugging experience on FPGA platforms.
Ability to debug processor designs on FPGA platforms.
Experience with Linux-based open-source software development.
Conscientious and thorough approach to design verification and system validation.
Thorough understanding of high-level verification-flow methodology, including test-plan generation, test generation, failure analysis, coverage analysis, and closure.
Good interpersonal skills for listening to diverse viewpoints and influencing people across disciplines.
Strong dedication to product quality.
Familiarity with, or ability to learn, non-standard verification languages and methodologies such as Scala and Chisel.
Culture & Benefits
Collaborative, cross-functional environment focused on innovation and product quality.
Inclusive workplace committed to diversity and equal opportunity.
Employment is contingent on successful background and reference checks.
Employment is contingent on authorization to access export-controlled technology under applicable laws, or successful acquisition of required export licenses or approvals.
Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →