Senior Engineer, ASIC Digital Design (System IP Verification)

Location: Hsinchu, Taiwan

Company

hirify.global manufactures essential semiconductors for high-growth markets, including AI, with operations across the U.S., Europe, and Asia.

What you will do

• Learn system IP architecture and intended behavior, contribute to specification reviews and verification planning, and verify functional, stress, and corner-case scenarios.
• Develop and maintain SystemVerilog/UVM verification content, including tests, sequences, monitors, scoreboards, reference models, assertions, checkers, and functional coverage.
• Run simulations and regressions; analyze logs, waveforms, and coverage results; isolate issues across RTL, testbench, protocol, configuration, clock/reset, and subsystem-interaction boundaries.
• Apply Python, C/C++, or shell scripting to improve test generation, verification automation, regression analysis, data analysis, and debugging productivity.
• Collaborate with architecture, RTL design, formal verification, modeling, software, infrastructure, and processor/subsystem verification teams.
• Document verification intent, implementation, results, and lessons learned; participate in technical reviews, knowledge sharing, and continuous improvement.

Requirements

• Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or a closely related field.
• Strong academic foundation in digital logic, digital IC design, computer architecture, VLSI, embedded systems, or a related area.
• Hands-on programming or hardware-description experience in at least one of Verilog/SystemVerilog, C/C++, or Python.
• Basic understanding of RTL design, simulation, and debugging concepts, with the ability to analyze technical problems systematically.
• Ability to learn unfamiliar concepts and clearly communicate technical assumptions, findings, and open questions in written and spoken English.
• Ability to work constructively with engineers across functions and geographical locations.

Nice to have

• Thesis, research, internship, or project experience involving computer or processor architecture, RISC-V, cache or memory systems, interconnect/NoC, SoC integration, FPGA, or digital verification.
• Exposure to SystemVerilog/UVM, constrained-random verification, assertions/SVA, functional or code coverage, formal verification, performance modeling, or processor/subsystem-level validation.
• Familiarity with Linux, Git, and EDA simulation or debug tools such as VCS/Verdi, Xcelium/SimVision, Questa, Verilator, or equivalent tools.
• Experience applying Python, C/C++, or shell scripting to verification automation.
• Interest in developing deeper expertise in cache coherency, memory ordering, interconnect protocols, low-power verification, functional safety/security, or verification automation.

Culture & Benefits

• Technical mentoring from experienced engineers while developing practical verification skills.
• Collaboration with global architecture, RTL design, modeling, formal verification, software, and system validation teams.
• Multicultural and inclusive workplace focused on respect, diversity, security, longevity, and sustainability.
• Full-time employment subject to local background checks, medical screenings where applicable, and local laws.