Senior Staff Device Engineer (Semiconductor)

Location: Taipei, Taiwan. The role requires satisfactory proof of the right to work in Taiwan.

Company

hirify.global develops low-cost, low-power programmable logic solutions, including FPGA, CPLD, and programmable power management devices, for customers worldwide.

What you will do

• Analyze circuit failures and yield anomalies from the circuit level down to transistor-level behavior and specific fab process steps using CAD navigation and circuit/layout knowledge.
• Study process design rules, DRC, DFM guidelines, device construction, transistor characteristics, and SPICE model corner coverage to identify structural and layout-dependent weak points.
• Design test keys and test chips for transistor characterization and reliability-limit monitoring, and modify DRC screening with CAD teams where needed.
• Own sustaining activities including yield improvement, process-window optimization, SPC monitoring, and analysis of WAT, inline, sort, bitmap, and final-test data.
• Translate electrical test failures into layout-level regions for de-layering, nanoprobing, SEM, and TEM analysis, coordinating fault isolation with internal and foundry FA teams.
• Support customer-facing quality escalations, including 8D and CAR responses, and advise Design and Layout teams on changes that improve yield and reliability.

Requirements

• M.S. or Ph.D. in Electrical Engineering, Microelectronics, Materials Science, or a related field, plus 10+ years of relevant experience in a fabless semiconductor or foundry ecosystem.
• Strong knowledge and hands-on experience in transistor-level characterization, compact modeling, and semiconductor reliability mechanisms including HCI, NBTI, and TDDB.
• Full proficiency with industry-standard CAD tools such as Cadence Virtuoso and Synopsys for schematic capture, layout verification including DRC/LVS, and physical design analysis.
• Proven ability to identify physical weak points in product layouts and link them directly to fab manufacturing constraints.
• Experience with WAT parametric analysis, yield engineering, SPC, failure diagnosis and analysis coordination, and process-window optimization.
• Understanding of semiconductor product test flow and ability to work effectively with manufacturing test and product engineering teams.
• Successful background and reference checks and satisfactory proof of the right to work in Taiwan.

Nice to have

• Familiarity with Lattice FPGA architecture or programmable logic products.

Culture & Benefits

• Work in an international organization focused on R&D, product innovation, and customer service.
• Collaborate across Design, Layout, Product Engineering, Product Test, Failure Analysis, CAD, and foundry teams.
• Operate in a fast-paced, results-oriented, team-first environment.
• Lattice provides a comprehensive compensation and benefits program.
• The organization emphasizes diversity of individuals, ideas, perspectives, insights, and values.