Principal Engineer, Physical Design (Semiconductor)
Контакты
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Taiwan
pythonphysical designedatclstatic timing analysissynthesisplace and routertl to gdsii
Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
Пожаловаться
Зарплата и рынок
ЗП не указана
На похожих ролях по рынку
$164к$187кмедиана$193к
50 в выборке
На СНГ рынке: $1.9к/мес ($1.8к - $3к)
86
Хорошая вакансия
развернуть
В Company hidden предлагают четко очерченную роль уровня principal с работой над передовыми чипами и участием в бонусной и акционной программах. Основные вопросы для решения - зарплата не раскрыта, а доступ к технологиям зависит от экспортных ограничений.
Кликните для подробной информации
Без зарплатной вилкиЭкспортные ограниченияЧеткая зона ответственностиАктуальные технологииБонусы и акции
Оценка от Hirify AI
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Подключить Plus
Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Principal Engineer, Physical Design (Semiconductor): Developing next-generation physical design methodologies and automation flows for high-performance processor and ASIC chips with an accent on RTL-to-GDSII implementation, timing closure, and advanced EDA technologies. Focus on architecting scalable implementation flows, resolving complex physical design challenges, and leading collaboration across RTL, verification, CAD, and global engineering teams.
Location: Hsinchu City, Taiwan; full-time onsite role.
Company
hirify.global develops semiconductor solutions and custom Processor/ASIC products for enterprise, cloud and AI, carrier, server, 5G/6G, automotive, and networking applications.
What you will do
Architect and lead next-generation physical design methodologies and automation flows.
Provide technical leadership for RTL-to-GDSII implementation, including synthesis, floorplanning, place and route, clock tree synthesis, and timing closure.
Collaborate with global RTL, verification, CAD, and other cross-functional teams.
Mentor senior and junior engineers and promote physical design best practices.
Evaluate EDA tools and technologies and represent physical design in technical and roadmap discussions.
Requirements
Bachelor’s, Master’s, or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
10+ years of progressive experience in back-end physical design and verification, including leadership roles.
Deep understanding of RTL-to-GDSII flows, including synthesis, place and route, clock tree synthesis, and timing closure.
Strong expertise in static timing analysis tools such as PrimeTime or Tempus, and power/signal integrity tools such as Voltus or RedHawk.
Proficiency in Python, Perl, Tcl, and Makefile for automation and flow development.
Demonstrated experience developing and deploying physical design methodologies and flows.
Strong communication and collaboration skills, including mentoring junior engineers and influencing cross-functional teams.
Nice to have
Experience working with EDA vendors and evaluating new tools and technologies.
Culture & Benefits
Collaborative, transparent, and inclusive work environment.
Competitive compensation and benefits.
Eligibility for bonus and equity plans, including a new-hire equity grant and annual equity refreshers.
Resources and support for professional growth and development.
Employment is subject to eligibility for access to export-controlled technology; some applicants may require an export license review.
Hiring process
Interviews assess individual experience, thought process, and communication skills in real time.
AI tools, transcription applications, automated answer generators, and automated note-taking bots are prohibited during interviews.
Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →