Staff Design Verification Engineer (CXL)

Location: Boston, Massachusetts, United States. Proof of the right to work in the United States of America is required. Access to export-controlled technology is subject to applicable authorization or licensing requirements.

Company

hirify.global develops high-performance RISC-V compute platforms for data-intensive applications, including AI, automotive, data center, mobile, and consumer technologies.

What you will do

• Drive verification of cache-coherent interconnect subsystems, interface boundaries, protocol adaptation layers, and bridge paths, with emphasis on CXL flows.
• Develop reusable SystemVerilog and UVM environments, checkers, scoreboards, assertions, stimulus, and coverage models.
• Create directed and constrained-random scenarios for coherency, concurrency, ordering, credits, arbitration, latency, bandwidth, QoS, flow control, and error handling.
• Collaborate with architecture, RTL, formal, and software teams to review specifications and resolve ambiguities.
• Analyze failures, identify root causes across specifications, RTL, and testbenches, and drive durable fixes.
• Improve verification methodology and automation while mentoring engineers and raising quality across the interconnect effort.

Requirements

• BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 7+ years of ASIC or SoC design verification experience owning complex block- or subsystem-level verification.
• Strong knowledge of CXL and at least one of CHI, ACE, AXI, or a similar high-performance interconnect standard.
• Hands-on experience with SystemVerilog, UVM, test plans, assertions, coverage models, scoreboards, and debug workflows.
• Strong understanding of cache-coherent systems, on-chip interconnects, memory subsystems, ordering, and flow-control semantics.
• Strong scripting, automation, debugging, and cross-functional communication skills, including Python or a similar language.

Nice to have

• Experience verifying coherent interconnect, cache, or memory-subsystem IP in high-performance SoCs.
• Experience with protocol-conversion or bridge-heavy subsystems involving CXL adaptation.
• Experience with formal verification, performance-oriented verification, emulation, or FPGA-assisted debugging.
• Experience mentoring engineers and influencing verification quality beyond direct ownership.

Culture & Benefits

• Cross-functional collaboration across architecture, RTL, formal, verification, and software teams.
• Full-time employment with a comprehensive benefits package that may include healthcare and retirement plans.
• Paid time off and potential variable or incentive compensation and equity.
• Employment is contingent on successful background and reference checks, employment eligibility verification, and export-control authorization.