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Design Verification Engineer (Silicon)

141 910 - 200 340$
Формат работы
hybrid
Тип работы
fulltime
Грейд
middle/senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify RU Global, списка компаний с восточно-европейскими корнями
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Описание вакансии

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TL;DR

Design Verification Engineer (Silicon): Developing and executing verification plans for next-generation interconnect and chassis IPs with an accent on UVM-based testbench development and coverage-driven verification. Focus on building reusable verification components, analyzing simulation failures, and leveraging AI-assisted workflows to ensure first-pass silicon success.

Location: Must be based in the US (Santa Clara, CA). This role follows a hybrid work model.

Salary: $141,910–$200,340 USD

Company

hirify.global is a global leader in data-driven engineering, providing scalable solutions across product enablement, custom ASIC, and foundry services.

What you will do

  • Develop and execute verification plans and testbenches for interconnect and chassis IP at the subsystem level.
  • Build reusable verification components, checkers, and constrained-random tests to improve coverage.
  • Collaborate with architecture, design, and software teams on spec reviews, bug triage, and closure.
  • Analyze simulation failures and drive root-cause fixes with clear technical communication.
  • Contribute to functional coverage planning and quality signoff under technical leadership.
  • Improve verification automation, regression quality, and development efficiency using AI-assisted tools.

Requirements

  • BS/MS in Electrical Engineering, Computer Science, or related field.
  • 3+ years of relevant experience in design verification.
  • Hands-on coding experience in SystemVerilog, C/C++, and Python.
  • Strong foundation in UVM/ABV and simulation-based verification methodologies.
  • Experience with AI-assisted development tools for coding and debugging.
  • Must be eligible to work in the United States.

Nice to have

  • Exposure to bus protocols like AMBA AXI/ACE/CHI, PCIe, CXL, or UCIe.
  • Understanding of cache coherency and memory consistency models.
  • Experience with formal verification tools like JasperGold or VC Formal.
  • Familiarity with emulation or FPGA-based verification.

Culture & Benefits

  • Competitive total compensation package including pay and stock bonuses.
  • Comprehensive health and retirement benefit programs.
  • Hybrid work model offering flexibility between on-site and off-site work.
  • Access to industry-leading engineering tools and methodologies.

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