Principal Verification Engineer (FPGA)

Location: Dublin, Ireland

Company

hirify.global is a global technology company developing semiconductor products, including secure, low-power FPGA devices.

What you will do

• Verify complex subsystems and SoCs using constrained-random, formal, and C-based verification methodologies.
• Develop and maintain reusable UVM-based test benches and verification environments.
• Perform RTL, power-aware, gate-level, emulation, hardware prototyping, and post-silicon verification and debug.
• Apply AI/ML-enabled verification methodologies and automate verification flows.
• Collaborate with architecture, design, emulation, and hardware prototyping teams to establish unified verification methods and support first-silicon success.
• Mentor junior team members and contribute to cross-functional engineering work.

Requirements

• 8+ years of experience in functional verification of complex SoC designs.
• Expertise in SystemVerilog, UVM, formal verification, methodology development, and tool automation.
• Understanding of ARM or RISC-V SoC architectures and at least two relevant domains, such as CPU subsystems, PCIe, DDR/LPDDR, MIPI, Ethernet MAC, USB, or security and cryptography IP.
• Experience with AI/ML-driven EDA tools, Python, TCL/TK, C/C++, and verification flow integration.
• Exposure to FPGA-based acceleration platforms, simulation and emulation flows, post-silicon debug, and Siemens, Cadence, or Synopsys verification suites.
• BS or MS in Electrical or Electronic Engineering, plus strong debugging, communication, and collaboration skills.

Nice to have

• Strong understanding of FPGA architecture.
• Experience with coverage-driven verification using ML-based optimizations.
• Knowledge of the complete SoC RTL-to-GDS-to-silicon release flow.

Culture & Benefits

• Work in a large global organization with a focus on trust, empowerment, respect, diversity, and communication.
• Access career development through Leadership Passage Programs and employee development initiatives.
• Collaborate with global cross-functional engineering teams.
• Travel requirement: 0%–25%.