Senior Staff Design Verification Engineer (Memory Sub-System)

Location: Must be based in Santa Clara, CA

Salary: $134,390 - $201,300 per annum

Company

hirify.global is a leading semiconductor solutions provider building the essential infrastructure for data, cloud, and AI architectures.

What you will do

• Develop and execute comprehensive verification plans for DDR, LPDDR, and HBM memory interfaces.
• Build and enhance UVM/System Verilog-based verification environments, test benches, and checkers.
• Perform protocol-level verification for memory controllers and PHY interfaces.
• Analyze and debug simulation failures to identify root causes and drive resolution.
• Collaborate with design, architecture, and firmware teams to ensure coverage closure and spec compliance.
• Contribute to coverage-driven verification including functional, code, and assertion coverage.

Requirements

• Bachelor’s or master’s degree in electrical or computer engineering.
• 5-10 years of experience in ASIC/SoC verification.
• Strong knowledge of DDR, LPDDR, or HBM protocols and architecture.
• Expertise in System Verilog and UVM methodology.
• Must be eligible to access export-controlled information under U.S. law.
• Solid understanding of digital design fundamentals.

Nice to have

• Knowledge of JEDEC standards.
• Experience with assertion-based verification (SVA).
• Exposure to performance modeling and traffic generation.
• Experience with emulation platforms like Palladium or Veloce.
• Scripting skills in Python, Perl, or Shell.

Culture & Benefits

• Comprehensive financial well-being programs including an employee stock purchase plan.
• Robust family support and mental health resources.
• Commitment to professional growth and leadership development.
• Inclusive work environment with a focus on long-term innovation.