Digital Verification Engineer (Verilog/SystemVerilog)

Location: Austin (Oakhill, Office), United States

Salary: $124,800 per year

Company

hirify.global develops semiconductor products and technologies.

What you will do

• Collaborate with architecture, systems, and design teams to understand product requirements and develop verification plans.
• Develop functional digital verification plans, test cases, verification IP, testbench components, and simulation models.
• Design, implement, and improve UVM test benches for IP, sub-system, and SoC-level verification.
• Run functional simulations, coverage analysis, and regression testing; identify coverage gaps and develop strategies to improve code coverage.
• Perform design and silicon debugging using development boards and lab equipment.
• Develop scripts and automation to improve coverage reports and support product release.

Requirements

• Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, a foreign equivalent, or a related field.
• Knowledge of computer architecture, digital integrated circuit design, and microprocessor system design.
• Experience with Verilog, SystemVerilog, and formal verification.
• Programming experience with Python or C/C++.
• Knowledge of SQL, Jenkins, Informatica data warehouses, troubleshooting, and debugging.

Culture & Benefits

• Full-time employment in an office-based Austin location.
• Collaboration across architecture, systems, design, and other functional groups.
• Equal opportunity employment and reasonable accommodations for qualified individuals with disabilities.