Senior Verification Engineer (ASIC)

TL;DR

Senior Verification Engineer (ASIC): Leading the development of scalable verification strategies and test environments for complex SoCs with an accent on UVM methodologies and coverage-driven verification. Focus on architecting verification plans, resolving pre-silicon bugs, and mentoring junior engineers to ensure high-quality semiconductor product delivery.

Location: Must be based in Canada. This role is fully home-based with occasional site visits required.

Salary: CAD 153,910–217,280

Company

hirify.global is a global leader in semiconductor technology, driving innovation in computing and data-centric solutions.

What you will do

• Define and implement scalable verification plans, test benches, and environments for blocks, subsystems, and SoCs.
• Lead technical reviews with design and architecture teams to validate verification plans and proofs.
• Execute simulation models to verify designs, analyze power and performance, and identify bugs.
• Investigate, root cause, and debug issues in the pre-silicon environment.
• Collaborate with cross-functional teams including RTL, physical design, and post-silicon teams.
• Mentor junior engineers and foster a collaborative technical environment.

Requirements

• Must be based in Canada and have legal authorization to work there.
• Bachelor's degree in electrical engineering, computer engineering, computer science, or related STEM field.
• 5+ years of experience in ASIC/FPGA design verification.
• Proficiency in UVM and/or Formal based verification architectures.
• Experience with industry-standard protocols (AMBA AXI/CHI/APB) and simulators like VCS or Xcelium.
• Strong skills in scripting languages including Python, TCL, and Shell.

Nice to have

• Graduate degree in a relevant STEM field with 8+ years of total experience.
• Experience with low power verification (UPF) and protocols like PCIe, DDR, or Ethernet.
• Knowledge of processor-based verification using C/C++.
• Experience with 3rd party VIPs and formal verification techniques.

Culture & Benefits

• Commitment to a culture of accessibility and inclusive hiring practices.
• Opportunities to work on cutting-edge semiconductor technology and next-generation chip development.
• Collaborative environment focused on innovation and technical leadership.
• Support for professional growth through mentorship and complex project exposure.