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10 часов назад

Principal Digital Design Engineer (AI Fabric)

185 000 - 230 000$
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
Principal Digital Design Engineer (AI Fabric) (Digital Design/AI Infrastructure): Architecting and implementing complex digital blocks and subsystems for high-performance connectivity solutions with an accent on micro-architecture, RTL implementation, timing closure, and DFT. Focus on owning blocks from architecture through GDS, collaborating on verification and silicon bring-up, and driving advanced CMOS designs to production.

Location: San Jose, CA, United States

Salary: $185,000–$230,000 USD gross annual base salary

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions and a software suite integrating CXL, Ethernet, NVLink, PCIe, and UALink technologies.

What you will do

  • Define micro-architectures and implement complex digital blocks and subsystems.
  • Own block-level design from architecture through GDS and drive designs to production.
  • Collaborate with verification teams on test plans, coverage closure, and complex issue debugging.
  • Lead timing closure and implement Design-for-Test features for high-performance designs.
  • Work with post-silicon teams on silicon bring-up, debugging, and failure analysis.
  • Mentor junior engineers and improve silicon development processes.

Requirements

  • Bachelor’s degree in electrical engineering or equivalent and 8+ years of hands-on experience developing complex SoC or silicon products in server, storage, or networking markets.
  • Experience with architecture definition, micro-architecture, RTL coding, functional simulation, synthesis, timing closure, gate-level simulation, and DFT implementation.
  • Production experience with advanced CMOS nodes of 7nm or smaller.
  • Deep expertise in at least one high-speed protocol, such as PCIe, Ethernet, InfiniBand, or DDR.
  • Experience integrating and verifying third-party IP, using Cadence and/or Synopsys digital design flows, and working with UVM-based verification methodologies.
  • Strong cross-functional communication, self-direction, adaptability, and ability to balance multiple priorities.

Nice to have

  • Experience delivering multiple high-performance designs to production in data-center environments.
  • Collaboration with embedded firmware teams and understanding of firmware development constraints.
  • Familiarity with embedded processor subsystems such as RISC-V or Arm.
  • Contributions to design methodology, CAD automation, or design infrastructure.

Culture & Benefits

  • Collaborative work across verification, physical design, DFT, post-silicon, and firmware teams.
  • Work with global teams in a fast-paced environment.
  • Inclusive environment encouraging applications from people with diverse backgrounds and experiences.

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