Principal Digital Design Engineer (AI Infrastructure)

Location: San Jose, California, United States

Salary: $185,000–$230,000 per year, depending on experience, level, and business need. The role may also include discretionary bonuses, incentives, and benefits.

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions and its COSMOS software suite, supporting hyperscalers and ecosystem partners.

What you will do

• Architect and implement complex digital blocks and subsystems, defining micro-architecture and driving RTL implementation.
• Optimize power, performance, and area for silicon technologies better than 7nm.
• Lead timing closure and implement Design-for-Test features.
• Drive designs through production, maintaining quality, schedule, and delivery accountability.
• Collaborate with verification, physical design, DFT, and post-silicon teams on test plans, coverage closure, IP integration, sign-off, silicon bring-up, and debug.
• Mentor junior engineers and improve silicon development methodologies and CAD automation.

Requirements

• Bachelor’s degree in Electrical Engineering or equivalent.
• 10+ years of hands-on experience developing complex SoC or silicon products in server, storage, and/or networking markets.
• Expertise in architecture definition, micro-architecture, RTL coding, functional simulation, and synthesis.
• Strong understanding of timing closure, gate-level simulation, and DFT implementation.
• Deep expertise in at least one high-speed protocol, including PCIe, CXL, Ethernet, DDR, or a similar technology.
• Production experience with advanced CMOS nodes of 7nm or smaller, plus proficiency with Cadence and/or Synopsys digital design flows.

Nice to have

• Master’s degree in Electrical Engineering or a related field.
• Experience delivering multiple high-performance designs to production in data-center environments.
• Collaboration experience with embedded firmware teams and familiarity with RISC-V, Arm, or similar processor subsystems.
• Contributions to design methodology, CAD automation, or design infrastructure.

Culture & Benefits

• Work on connectivity technologies for AI infrastructure and products deployed by leading hyperscalers.
• Collaborative environment involving verification, physical design, DFT, firmware, and post-silicon teams.
• Opportunity to contribute to high-performance silicon and advanced semiconductor technology.
• Potential eligibility for discretionary bonuses, incentives, and benefits.
• Inclusive workplace encouraging applications from people with diverse backgrounds and experiences.