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13 часов назад

ATE Solution Test Engineer (FPGA)

118 900 - 172 000$
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
ATE Solution Test Engineer (FPGA): Developing and sustaining scalable automated test solutions and production test programs for FPGA wafer sort and final test with an accent on semiconductor characterization, production limits, and manufacturing readiness. Focus on optimizing yield and test time, debugging silicon and tester hardware, and supporting product execution from NPI through high-volume manufacturing.

Location: San Jose, California, United States

Salary: $118,900–$172,000 USD per year for the Bay Area California region

Company

hirify.global is an independent FPGA solutions provider focused on programmable technologies for AI, cloud, networking, and edge markets.

What you will do

  • Develop, validate, and maintain ATE test methods and production test programs for wafer sort and final test using Teradyne and/or Advantest platforms.
  • Own product test development across NPI, silicon bring-up, characterization, qualification, production ramp, and sustaining engineering.
  • Analyze silicon performance across process, voltage, and temperature corners to establish production limits and optimize guardbands.
  • Drive yield improvement, test-time reduction, defect escape prevention, and test optimization through data analysis.
  • Debug silicon, testers, test hardware, and manufacturing issues.
  • Collaborate with Design, DFT, Validation, Reliability, Package Engineering, Manufacturing, and OSAT partners while supporting production releases and manufacturing transfers.

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline.
  • 5+ years of experience developing ATE test programs and methods for complex semiconductor products using Teradyne and/or Advantest.
  • 5+ years of experience with semiconductor test methodologies, silicon characterization, wafer sort, final test, and high-volume manufacturing flows.
  • Experience with DFT architectures including Scan, MBIST, JTAG, Boundary Scan, and ATPG.
  • Experience with production test hardware such as probe cards, load boards, sockets, and ATE interface hardware.
  • Programming or scripting experience with Python, Perl, C++, or similar languages; experience with JMP or equivalent statistical analysis tools; and 3+ years in Agile environments using version control.

Culture & Benefits

  • Regular full-time position on Shift 1 in the United States.
  • Incentive opportunities based on individual and company performance.
  • Applicants must be eligible for required U.S. export authorizations.
  • Artificial intelligence may be used to screen, assess, or select applicants.

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