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Principal ASIC Test Development Engineer (DFT)

153 500 - 291 500$
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Principal ASIC Test Development Engineer (DFT/2.5D SiP): Developing testability strategies and DFT solutions for ASICs, memories, and 2.5D SiPs across ATE and system-level environments with an accent on test coverage, manufacturability, and post-silicon validation. Focus on creating advanced fault models and test modes, diagnosing supplier failures, integrating diagnostics, and influencing ASIC manufacturing tests.

Location: Hybrid, with an expectation of working an average of two days per week from an HPE office in Sunnyvale, California; Houston, Texas; or Westford, Massachusetts.

Annual base salary: USD 153,500–291,500 in Massachusetts; USD 153,500–310,500 in California; USD 135,000–310,500 in Texas. Variable incentives may also be offered.

Company

hirify.global is a global edge-to-cloud technology company developing solutions that connect, protect, analyze, and manage data and applications.

What you will do

  • Develop test strategies and Design-for-Test solutions for ASICs, memories, and 2.5D SiPs across ATE and system-level environments.
  • Enable DFT features with design teams, validate them on ATE, integrate diagnostics, and implement manufacturing tests.
  • Own ASIC test requirements, phase-exit validation, advanced test modes, fault coverage, manufacturability, and continuous improvement.
  • Resolve ASIC issues and No-Trouble-Found supplier problems through wafer, package, and system test correlation and custom ATE-level tests.
  • Collaborate with ASIC, physical design, software, diagnostics, hardware, manufacturing, supplier, and contract manufacturing teams.
  • Influence supplier testing and contribute to IEEE 1149, IEEE 1687, P1838, and JC-42 standards activities.

Requirements

  • Principal or Distinguished Engineer expertise with 15+ years of experience in ASIC, memory, and 2.5D SiP testability and DFT.
  • Advanced knowledge of MBIST, IOBIST, LBIST, JTAG, scan/ATPG, and IEEE 1687.
  • Strong experience with ASIC DFT implementation, post-silicon validation, debug, and diagnostic integration.
  • Experience with high-performance ASICs, TSV, HBM DRAM, 2.5D, and 3D IC semiconductor test challenges.
  • Experience working with ASIC suppliers, IP and EDA vendors, SiP ecosystem partners, and contract manufacturers.
  • BS, MS, or PhD in Electrical Engineering, with strong communication, collaboration, program management, and influencing skills.

Culture & Benefits

  • Hybrid work model with office collaboration.
  • Health, financial, and emotional wellbeing benefits for employees and their families.
  • Personal and professional development programs supporting career growth and internal mobility.
  • Inclusive workplace that values varied backgrounds and individual uniqueness.

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