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ΠΎΠ±Π½ΠΎΠ²Π»Π΅Π½ΠΎ 9 часов Π½Π°Π·Π°Π΄

Principal ASIC Test Development Engineer

135Β 000 - 310Β 500$
Π€ΠΎΡ€ΠΌΠ°Ρ‚ Ρ€Π°Π±ΠΎΡ‚Ρ‹
hybrid
Π’ΠΈΠΏ Ρ€Π°Π±ΠΎΡ‚Ρ‹
fulltime
Π“Ρ€Π΅ΠΉΠ΄
senior
Английский
b2
Π‘Ρ‚Ρ€Π°Π½Π°
US
Вакансия ΠΈΠ· списка Hirify.GlobalВакансия ΠΈΠ· Hirify Global, списка ΠΌΠ΅ΠΆΠ΄ΡƒΠ½Π°Ρ€ΠΎΠ΄Π½Ρ‹Ρ… tech-ΠΊΠΎΠΌΠΏΠ°Π½ΠΈΠΉ
Для мэтча ΠΈ ΠΎΡ‚ΠΊΠ»ΠΈΠΊΠ° Π½ΡƒΠΆΠ΅Π½ Plus

ΠœΡΡ‚Ρ‡ & Π‘ΠΎΠΏΡ€ΠΎΠ²ΠΎΠ΄

Для мэтча с этой вакансиСй Π½ΡƒΠΆΠ΅Π½ Plus

ОписаниС вакансии

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TL;DR
Principal ASIC Test Development Engineer (DFT/ATE): Developing testability solutions and manufacturing test strategies for ASICs, memories, and 2.5D SiPs with an accent on DFT implementation, high test coverage, and post-silicon validation. Focus on integrating MBIST, LBIST, JTAG, scan/ATPG, and IEEE 1687 capabilities, solving supplier ASIC failures, and improving manufacturability across ATE and system-level environments.

Location: Hybrid, with an expectation of working an average of 2 days per week from an HPE office in the United States

Salary: USD 135,000–310,500 annual base salary, with ranges varying by state and geographic location. Variable incentives may also be offered.

Company

hirify.global is an edge-to-cloud technology company developing solutions that connect, protect, analyze, and manage data and applications.

What you will do

  • Develop ASIC and 2.5D SiP test strategies and DFT solutions supporting high component and system test coverage.
  • Enable DFT features with design teams, validate designs on ATE, integrate diagnostics, and implement manufacturing tests.
  • Develop DFT IP and advanced test modes with internal cross-functional teams, ASIC suppliers, and external partners.
  • Investigate ASIC quality issues and no-trouble-found supplier failures using wafer, package, ATE, and system-level testing.
  • Own ASIC test requirements, phase-exit validation, fault coverage, manufacturability objectives, and continuous improvement.
  • Influence supplier production testing and represent ASIC test authority across design, software, hardware, manufacturing, and quality teams.

Requirements

  • Principal or Distinguished Engineer-level expertise with 15+ years of experience in ASIC, memory, and 2.5D SiP testability and DFT.
  • Strong knowledge of MBIST, IOBIST, LBIST, JTAG, scan/ATPG, and IEEE 1687.
  • Experience with ASIC DFT implementation, post-silicon validation, debug, and diagnostic integration.
  • Experience with high-performance ASICs, TSV, HBM DRAM, 2.5D and 3D IC test challenges.
  • Broad experience working with ASIC suppliers, IP and EDA vendors, SiP ecosystem partners, and contract manufacturers.
  • BS, MS, or PhD in Electrical Engineering, plus strong communication, collaboration, and program management skills.

Culture & Benefits

  • Hybrid work model with flexibility to manage work and personal needs.
  • Comprehensive health, financial, and emotional wellbeing benefits for employees and their families.
  • Personal and professional development programs supporting career growth and subject-matter expertise.
  • Inclusive work environment that values varied backgrounds and individual uniqueness.

Π‘ΡƒΠ΄ΡŒΡ‚Π΅ остороТны: Ссли Ρ€Π°Π±ΠΎΡ‚ΠΎΠ΄Π°Ρ‚Π΅Π»ΡŒ просит Π²ΠΎΠΉΡ‚ΠΈ Π² ΠΈΡ… систСму, ΠΈΡΠΏΠΎΠ»ΡŒΠ·ΡƒΡ iCloud/Google, ΠΏΡ€ΠΈΡΠ»Π°Ρ‚ΡŒ ΠΊΠΎΠ΄/ΠΏΠ°Ρ€ΠΎΠ»ΡŒ, Π·Π°ΠΏΡƒΡΡ‚ΠΈΡ‚ΡŒ ΠΊΠΎΠ΄/ПО, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡ‚Π΅ этого - это мошСнники. ΠžΠ±ΡΠ·Π°Ρ‚Π΅Π»ΡŒΠ½ΠΎ ΠΆΠΌΠΈΡ‚Π΅ "ΠŸΠΎΠΆΠ°Π»ΠΎΠ²Π°Ρ‚ΡŒΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡˆΠΈΡ‚Π΅ Π² ΠΏΠΎΠ΄Π΄Π΅Ρ€ΠΆΠΊΡƒ. ΠŸΠΎΠ΄Ρ€ΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β†’