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14 часов назад

Test Engineer (Semiconductor)

150 000 - 190 000$
Тип работы
fulltime
Грейд
middle
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Test Engineer (Semiconductor): Developing and scaling chip test engineering across DFT strategy, ATPG pattern generation, ATE bringup, and production test with an accent on wafer probe, final test, OSAT coordination, and silicon characterization. Focus on validating test programs across voltage, temperature, and frequency corners, analyzing yield data, and optimizing test flows for multiple chip programs.

Location: San Jose, CA, United States

Salary: $150,000–$190,000 per year, plus equity and benefits

Company

hirify.global is a fabless semiconductor startup developing energy-efficient processors for edge computing, embedded AI, and high-performance applications.

What you will do

  • Define DFT strategies and generate, validate, and deliver ATPG patterns for scan, MBIST, JTAG, and embedded memory testing.
  • Develop and debug STIL and PDL test programs on Advantest and Teradyne ATE platforms.
  • Support first-silicon bringup, load-board validation, and characterization across voltage, temperature, and frequency corners.
  • Define and manage wafer probe, final test, and bin-sort flows, including power sequencing and test-time optimization.
  • Coordinate test-program handoffs, pattern delivery, qualification, and acceptance criteria with foundries, OSATs, test houses, and design partners.
  • Track probe and final-test yield data, resolve anomalies, and coordinate test capacity planning and lot scheduling.

Requirements

  • 5+ years of semiconductor test engineering experience in a fabless or IDM environment.
  • Hands-on experience with DFT, including scan insertion, ATPG, MBIST, and JTAG boundary scan.
  • Experience generating and validating STIL patterns and managing test-pattern delivery packages.
  • ATE test-program development experience on Advantest or Teradyne platforms, including wafer probe, final test, and load-board bringup.
  • Ability to coordinate directly with external design partners and OSAT suppliers across multiple time zones.
  • Strong written and verbal communication skills.

Nice to have

  • Embedded memory characterization and programming experience, including non-volatile memory technologies.
  • Experience with high-speed serial interface testing, major EDA DFT tools, or processes at 28nm and below.
  • ATE yield analysis, test-time optimization, or test automation using Python or Perl.
  • Experience generating VCD from RTL simulation and porting it to STIL.

Culture & Benefits

  • Competitive compensation with meaningful equity.
  • 401(k) matching and company-paid benefits.
  • Paid parental leave.
  • Flexibility and support for personal and professional development.

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