Staff Engineer: STA Methodology & Sign-off Lead (Cadence Tempus)

Location: Bangalore, India

Company

hirify.global develops advanced AI hardware and software systems for efficient edge-to-cloud computing using next-generation in-memory computing technology.

What you will do

• Define and own full-chip SOC timing sign-off criteria, including MMMC definitions, derate strategies, and operating-condition mapping.
• Architect, deploy, and maintain STA and ECO flows that identify structural timing issues early in RTL and synthesis.
• Evaluate, qualify, and deploy EDA tool capabilities, with a strong emphasis on Cadence Tempus, to improve QoR and runtime efficiency.
• Build Tcl, Python, and Perl automation for SDC management, cross-domain timing audits, and ECO acceleration.
• Partner with Physical Design on CTS and floorplanning methodologies and guide DFT and RTL teams in resolving structural timing bottlenecks.

Requirements

• 8–11 years of hands-on VLSI design experience focused on STA methodology, flow development, and sign-off criteria.
• Experience with advanced process nodes, including 7nm, 5nm, or below.
• Deep expertise with industry-standard sign-off tools, preferably Cadence Tempus.
• Mastery of MMMC architecture, hierarchical ILM/ETM and flat timing strategies, and SDC validation.
• Strong understanding of waveform propagation, crosstalk, and statistical margining using LVF and POCV.
• B.Tech/M.Tech in Electrical, Electronics Engineering, or a related field, plus the ability to lead cross-functional methodology adoption.

Culture & Benefits

• Work in a fast-paced, high-growth environment focused on advanced AI computing.
• Collaborate across Architecture, CAD, RTL, DFT, and Physical Design teams.
• Own technical standards and methodology decisions with broad scope through tape-out.