12 ΡΠ°ΡΠΎΠ² Π½Π°Π·Π°Π΄
Junior Physical Design Engineer (Semiconductor)
ΠΡΡΡ & Π‘ΠΎΠΏΡΠΎΠ²ΠΎΠ΄
ΠΠ»Ρ ΠΌΡΡΡΠ° Ρ ΡΡΠΎΠΉ Π²Π°ΠΊΠ°Π½ΡΠΈΠ΅ΠΉ Π½ΡΠΆΠ΅Π½ Plus
ΠΠΏΠΈΡΠ°Π½ΠΈΠ΅ Π²Π°ΠΊΠ°Π½ΡΠΈΠΈ
Π’Π΅ΠΊΡΡ:
TL;DR
Junior Physical Design Engineer (Semiconductor): Driving the RTL-to-GDS physical implementation of advanced connectivity chips for AI infrastructure with an accent on synthesis, floorplanning, place and route, clock-tree synthesis, and signoff analysis. Focus on building backend methodologies, solving timing, power, area, and routing challenges in advanced process nodes, and automating EDA workflows with TCL or Python.
Location: Tel Aviv-Yafo, Tel Aviv District, Israel
Company
develops semiconductor-based connectivity solutions and software for rack-scale AI infrastructure, integrating technologies such as CXL, Ethernet, NVLink, PCIe, and UALink.
What you will do
- Contribute to the founding backend engineering team and help establish local execution standards and methodologies.
- Execute the physical implementation flow from synthesis through floorplanning, placement, routing, and clock-tree synthesis.
- Own macro-level implementation, including complex floorplanning and routing.
- Drive timing signoff, physical verification, reliability analysis, and logic equivalence checking.
- Collaborate with Architecture, Design, and DFT teams on advanced process nodes and high-speed connectivity designs.
- Develop scripting and automation to improve EDA workflows and engineering infrastructure.
Requirements
- Bachelorβs degree in Electrical Engineering or a related technical field.
- Foundational understanding of the RTL-to-GDS flow, including floorplanning, placement, and routing through academic or internship experience.
- Familiarity with advanced process technologies such as 7nm and below.
- Basic experience with STA, Logic Equivalence Checking, DRC, and EMIR analysis.
- Working knowledge of TCL or Python for simple automation and EDA tool-flow support.
Nice to have
- Full-chip implementation and integration experience.
- Knowledge of power and noise analysis, including SI/PI.
- Familiarity with DFT requirements and their impact on physical layout.
- Experience with Synopsys Fusion Compiler, ICC2, or Cadence Innovus.
- Background in high-speed interface designs or connectivity protocols.
Culture & Benefits
- Opportunity to help establish a new strategic R&D center and local engineering culture in Israel.
- Meaningful ownership of backend execution and methodology development for AI infrastructure chips.
- Inclusive environment encouraging applications from people with diverse backgrounds and experiences.
ΠΡΠ΄ΡΡΠ΅ ΠΎΡΡΠΎΡΠΎΠΆΠ½Ρ: Π΅ΡΠ»ΠΈ ΡΠ°Π±ΠΎΡΠΎΠ΄Π°ΡΠ΅Π»Ρ ΠΏΡΠΎΡΠΈΡ Π²ΠΎΠΉΡΠΈ Π² ΠΈΡ ΡΠΈΡΡΠ΅ΠΌΡ, ΠΈΡΠΏΠΎΠ»ΡΠ·ΡΡ iCloud/Google, ΠΏΡΠΈΡΠ»Π°ΡΡ ΠΊΠΎΠ΄/ΠΏΠ°ΡΠΎΠ»Ρ, Π·Π°ΠΏΡΡΡΠΈΡΡ ΠΊΠΎΠ΄/ΠΠ, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡΠ΅ ΡΡΠΎΠ³ΠΎ - ΡΡΠΎ ΠΌΠΎΡΠ΅Π½Π½ΠΈΠΊΠΈ. ΠΠ±ΡΠ·Π°ΡΠ΅Π»ΡΠ½ΠΎ ΠΆΠΌΠΈΡΠ΅ "ΠΠΎΠΆΠ°Π»ΠΎΠ²Π°ΡΡΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡΠΈΡΠ΅ Π² ΠΏΠΎΠ΄Π΄Π΅ΡΠΆΠΊΡ. ΠΠΎΠ΄ΡΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β
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