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12 часов Π½Π°Π·Π°Π΄

Junior Physical Design Engineer (Semiconductor)

Π’ΠΈΠΏ Ρ€Π°Π±ΠΎΡ‚Ρ‹
fulltime
Π“Ρ€Π΅ΠΉΠ΄
junior
Английский
b2
Π‘Ρ‚Ρ€Π°Π½Π°
Israel
Вакансия ΠΈΠ· списка Hirify.GlobalВакансия ΠΈΠ· Hirify Global, списка ΠΌΠ΅ΠΆΠ΄ΡƒΠ½Π°Ρ€ΠΎΠ΄Π½Ρ‹Ρ… tech-ΠΊΠΎΠΌΠΏΠ°Π½ΠΈΠΉ
Для мэтча ΠΈ ΠΎΡ‚ΠΊΠ»ΠΈΠΊΠ° Π½ΡƒΠΆΠ΅Π½ Plus

ΠœΡΡ‚Ρ‡ & Π‘ΠΎΠΏΡ€ΠΎΠ²ΠΎΠ΄

Для мэтча с этой вакансиСй Π½ΡƒΠΆΠ΅Π½ Plus

ОписаниС вакансии

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TL;DR
Junior Physical Design Engineer (Semiconductor): Driving the RTL-to-GDS physical implementation of advanced connectivity chips for AI infrastructure with an accent on synthesis, floorplanning, place and route, clock-tree synthesis, and signoff analysis. Focus on building backend methodologies, solving timing, power, area, and routing challenges in advanced process nodes, and automating EDA workflows with TCL or Python.

Location: Tel Aviv-Yafo, Tel Aviv District, Israel

Company

hirify.global develops semiconductor-based connectivity solutions and software for rack-scale AI infrastructure, integrating technologies such as CXL, Ethernet, NVLink, PCIe, and UALink.

What you will do

  • Contribute to the founding backend engineering team and help establish local execution standards and methodologies.
  • Execute the physical implementation flow from synthesis through floorplanning, placement, routing, and clock-tree synthesis.
  • Own macro-level implementation, including complex floorplanning and routing.
  • Drive timing signoff, physical verification, reliability analysis, and logic equivalence checking.
  • Collaborate with Architecture, Design, and DFT teams on advanced process nodes and high-speed connectivity designs.
  • Develop scripting and automation to improve EDA workflows and engineering infrastructure.

Requirements

  • Bachelor’s degree in Electrical Engineering or a related technical field.
  • Foundational understanding of the RTL-to-GDS flow, including floorplanning, placement, and routing through academic or internship experience.
  • Familiarity with advanced process technologies such as 7nm and below.
  • Basic experience with STA, Logic Equivalence Checking, DRC, and EMIR analysis.
  • Working knowledge of TCL or Python for simple automation and EDA tool-flow support.

Nice to have

  • Full-chip implementation and integration experience.
  • Knowledge of power and noise analysis, including SI/PI.
  • Familiarity with DFT requirements and their impact on physical layout.
  • Experience with Synopsys Fusion Compiler, ICC2, or Cadence Innovus.
  • Background in high-speed interface designs or connectivity protocols.

Culture & Benefits

  • Opportunity to help establish a new strategic R&D center and local engineering culture in Israel.
  • Meaningful ownership of backend execution and methodology development for AI infrastructure chips.
  • Inclusive environment encouraging applications from people with diverse backgrounds and experiences.

Π‘ΡƒΠ΄ΡŒΡ‚Π΅ остороТны: Ссли Ρ€Π°Π±ΠΎΡ‚ΠΎΠ΄Π°Ρ‚Π΅Π»ΡŒ просит Π²ΠΎΠΉΡ‚ΠΈ Π² ΠΈΡ… систСму, ΠΈΡΠΏΠΎΠ»ΡŒΠ·ΡƒΡ iCloud/Google, ΠΏΡ€ΠΈΡΠ»Π°Ρ‚ΡŒ ΠΊΠΎΠ΄/ΠΏΠ°Ρ€ΠΎΠ»ΡŒ, Π·Π°ΠΏΡƒΡΡ‚ΠΈΡ‚ΡŒ ΠΊΠΎΠ΄/ПО, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡ‚Π΅ этого - это мошСнники. ΠžΠ±ΡΠ·Π°Ρ‚Π΅Π»ΡŒΠ½ΠΎ ΠΆΠΌΠΈΡ‚Π΅ "ΠŸΠΎΠΆΠ°Π»ΠΎΠ²Π°Ρ‚ΡŒΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡˆΠΈΡ‚Π΅ Π² ΠΏΠΎΠ΄Π΄Π΅Ρ€ΠΆΠΊΡƒ. ΠŸΠΎΠ΄Ρ€ΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β†’