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14 часов назад

Technical Staff Engineer - Design

107 000 - 226 000$
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Canada
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Technical Staff Engineer - Design (SoC/IO): Developing storage and memory controller SoCs from initial concept through production with an accent on pad ring planning, bump pattern design, and PHY-level IO interfaces. Focus on generating physical design handoff deliverables, resolving package and system-level constraints, and supporting ASIC validation and silicon debug.

Location: Burnaby, Canada

Annual base salary: $107,000–$226,000

Company

hirify.global is a global semiconductor company developing products for data center, storage, memory, connectivity, and embedded computing applications.

What you will do

  • Plan and construct pad rings and bump patterns while aligning designs with package and system-level constraints.
  • Develop and maintain IO connectivity, pad ring definitions, and bump pattern designs throughout the product lifecycle.
  • Generate and validate pad ring DEF files, Verilog netlists, bump maps, and other physical design handoff deliverables.
  • Ensure IO and pad ring designs comply with design standards, package constraints, and implementation best practices.
  • Collaborate with architecture, product design, IP packaging, implementation, product engineering, technology development, and foundry teams.
  • Support verification, emulation, ASIC validation, and silicon debug by analyzing IO-related issues and driving improvements.

Requirements

  • Bachelor’s degree in electrical engineering and 12+ years of related experience.
  • Hands-on experience with pad ring planning, IO cell placement, and bump map or pattern definition for advanced SoC designs.
  • Knowledge of IO library cells, IO standards, and PHY-level interfaces including SerDes, DDR, PCIe, and CXL.
  • Experience with IO planning and implementation EDA tools such as Orbit IO, ISP, or equivalent.
  • Experience generating and validating pad ring DEF, IO netlist, and bump assignment deliverables for physical design handoff.
  • Working proficiency with Tcl and/or Python scripting, plus strong analytical, communication, and documentation skills.

Nice to have

  • Master’s degree in electrical engineering.
  • Understanding of JTAG and Boundary Scan, IEEE 1149.1, and TAP controller operation.
  • Exposure to RTL compilation, synthesis, Verilog, or SystemVerilog.
  • Experience with SVN, JIRA, or comparable project, versioning, and tracking tools.

Culture & Benefits

  • Continuous learning in a challenging engineering environment.
  • Health benefits beginning on the first day.
  • Retirement savings plans and an employee stock purchase program with a six-month look-back feature.
  • Total compensation includes base pay, restricted stock units, and quarterly bonuses.
  • Travel expectation is 0%–25%.

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