Technical Staff Engineer - Design (SoC)

Location: Burnaby, Canada

Annual base salary: $107,000–$226,000

Company

Global semiconductor technology company developing storage, memory, connectivity, and data center solutions for server, storage, and hyperscale data center applications.

What you will do

• Plan and construct pad rings and bump patterns while aligning designs with package and system-level constraints.
• Develop, implement, and maintain IO connectivity, pad-ring definitions, and bump-pattern designs throughout the design cycle.
• Generate and validate physical-design handoff deliverables, including pad-ring DEF files, Verilog netlists, bump maps, and implementation data.
• Ensure IO and pad-ring designs comply with design standards, package constraints, and implementation best practices.
• Collaborate with Architecture, Product Design, Internal IP Packaging, Implementation, Product Engineering, Technology Development, and Foundry teams to resolve technical issues.
• Support verification, emulation, ASIC validation, and silicon debugging by analyzing IO-related issues and driving design improvements.

Requirements

• B.S. degree in electrical engineering and 12+ years of related experience.
• Hands-on experience with pad-ring planning, IO-cell placement, and bump-map or bump-pattern definition for advanced SoC designs.
• Knowledge of IO library cells, IO standards, and PHY-level interfaces including SerDes, DDR, PCIe, and CXL.
• Experience with IO-planning and implementation EDA tools, such as Orbit IO, ISP, or equivalent.
• Experience generating and validating IO-connectivity deliverables, including pad-ring DEF files, IO netlists, and bump assignments, for physical-design handoff.
• Understanding of Foundation IP and Hard IP views, including RTL, LEF, and Liberty.
• Working proficiency in flow automation and scripting using Tcl and/or Python.
• Excellent analytical, written and verbal communication, and documentation skills.

Nice to have

• M.S. degree in electrical engineering.
• Basic understanding of DFT methodologies, particularly JTAG and Boundary Scan, IEEE 1149.1 architecture, and TAP-controller operation for post-silicon bring-up and SoC IO validation debugging.
• Exposure to RTL compilation and synthesis flows, including Verilog and SystemVerilog.
• Working knowledge of project-management, versioning, and tracking tools such as SVN and JIRA.

Culture & Benefits

• Work within a growing Data Center Solutions business unit serving server, storage, and hyperscale data center applications.
• Access to continuous learning and employee-development programs.
• Health benefits beginning on the first day.
• Retirement savings plans and an employee stock purchase program with a six-month look-back feature.
• Total compensation includes base pay, restricted stock units, and quarterly bonus payments.
• Travel requirement is 0%–25%.