Physical Design Engineering Director

Location: Toronto, Ontario, Canada; fully onsite.

Base salary: CAD 200,000–CAD 250,000, depending on experience, level, and business need. The role may also be eligible for discretionary bonus, incentives, and benefits.

Company

hirify.global provides rack-scale AI infrastructure through semiconductor connectivity solutions and software for hyperscalers, AI clusters, and data centers.

What you will do

• Lead, build, and mentor the Toronto physical design team for Signal Connectivity Group products.
• Own block- and top-level physical design implementation from floorplan through tapeout for retimer and signal conditioning ASICs.
• Drive synthesis, place-and-route, CTS, extraction, timing closure, EM-IR, DRC/LVS, equivalence checking, and final sign-off.
• Collaborate with RTL, DFT, STA, EMIR, verification, and IP vendor teams on design convergence and hard-macro integration.
• Establish physical design best practices, flow improvements, and quality checks across multiple concurrent programs.
• Coordinate methodology and design quality with global physical design teams in San Jose, Irvine, and Bangalore, while leading hiring, career development, and sprint planning.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field; a Master’s degree is preferred.
• 15+ years of experience in physical design implementation of complex SoCs at advanced nodes, including 7nm and below.
• 5+ years of experience leading teams or projects, with the ability to mentor and develop engineers.
• Hands-on expertise across synthesis, place-and-route, CTS, extraction, timing closure, EM-IR, DRC/LVS, and equivalence checking.
• Experience with Cadence Innovus and/or Synopsys Fusion Compiler or ICC2 and supporting toolchains.
• Strong scripting ability in Tcl, Python, and/or Perl.
• Ability to prioritize dynamic tasks, prepare for customer meetings, work with minimal guidance, and maintain a professional, entrepreneurial, open-minded, and customer-focused approach.
• Experience building and leading physical design teams, owning execution and team development for Signal Connectivity Group products.
• Experience collaborating with IP vendors on RTL and hard-macro integration, including placement constraints and routing guidelines.

Nice to have

• Deep understanding of high-speed SerDes physical layers, including equalization, CDR, and signal integrity considerations affecting physical design.
• Knowledge of physical-layer timing challenges in high-speed serial interfaces.
• Track record of building and scaling physical design teams through multiple tapeouts.
• Knowledge of agentic AI solutions for EDA automation.

Culture & Benefits

• Fully onsite work at the Toronto location.
• Potential eligibility for discretionary bonus, incentives, and benefits.
• Commitment to diverse ideas, backgrounds, and experiences, with encouragement for applicants from underrepresented groups, veterans, parents, and individuals with disabilities.