Digital Verification Engineer (SoC)

Location: San Francisco, Bay Area, Pittsburgh, PA, or Austin, TX

Salary: $130,000–$180,000 base salary, plus a 10% annual bonus and equity

Company

hirify.global develops energy-efficient computing hardware and software, including the Fabric architecture and Electron E1 processor, for AI and other general-purpose applications.

What you will do

• Develop and maintain UVM/SystemVerilog testbenches, sequences, and tests for SoC blocks and subsystems.
• Create verification plans from design specifications in collaboration with design and architecture teams.
• Write SystemVerilog assertions and functional coverage models, and drive code and functional coverage to closure.
• Debug simulation failures with designers using waveforms, logs, and design knowledge to identify root causes.
• Contribute to regression infrastructure, test automation, and dashboards tracking verification progress.
• Support gate-level simulation and other verification sign-off activities.

Requirements

• Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field.
• 4+ years of ASIC/SoC design verification experience, including multiple projects taken through tapeout.
• Hands-on experience building and extending UVM testbench components, including agents, scoreboards, and sequences, as well as constrained-random tests.
• Experience defining functional coverage and driving code and functional coverage closure at block or subsystem level.
• Working knowledge of SystemVerilog Assertions.
• Ability to independently debug simulation failures using waveforms, logs, and design knowledge.
• Proficiency in Python for test automation, log analysis, and regression flows.
• Ability to clearly report verification status and issues to the team.

Nice to have

• C/C++ experience for reference models or DPI-based verification.
• Exposure to formal verification using JasperGold or similar tools.
• Experience building or using AI agentic flows for design verification.
• Knowledge of computer architecture or dataflow architectures.
• Exposure to power-aware verification using UPF.

Culture & Benefits

• Opportunity to own verification work and influence products and processes during the transition from initial development to market release and scaled production.
• Competitive base salary, annual bonus, meaningful equity, and comprehensive benefits.
• 401(k) match and company-paid benefits.
• Paid parental leave and flexibility.
• Opportunities to grow technical skills and career as the company scales.