Design Verification Manager (Semiconductor)

Location: Onsite in Sunnyvale, California, United States, with the expectation of primarily working from an HPE office.

Salary: $174,000–$352,500 annual base salary in California, United States. Variable incentives may also be offered.

Company

hirify.global is a global edge-to-cloud technology company connecting, protecting, analyzing, and managing data and applications from edge to cloud.

What you will do

• Lead, mentor, and develop a team of design verification engineers while fostering technical excellence and collaborative accountability.
• Allocate engineering resources across multiple parallel chip and block schedules.
• Define verification strategies, infrastructure, execution plans, and testbench architecture for complex SoC and IP blocks.
• Drive advanced verification methodologies, functional metric tracking, automated flows, and verification across block, subsystem, and full-chip environments.
• Collaborate with Architecture, RTL Design, Physical Design, and Post-Silicon Validation teams to identify coverage gaps, debug system-level failures, and meet tape-out milestones.

Requirements

• 10+ years of deep, hands-on experience in pre-silicon ASIC/SoC design verification.
• 5+ years of dedicated engineering management or formal team leadership experience, including direct management of engineering headcount, performance reviews, and project delivery schedules.
• Bachelor’s degree in Electrical Engineering, Computer Science, Computer Engineering, or a closely related technical field.
• Expert-level fluency in SystemVerilog and Universal Verification Methodology (UVM) architecture.
• Proven experience building scalable UVM-compliant testbenches from scratch.
• Proven experience using formal methods to mathematically prove block-level assertions and identify corner-case bugs.
• Strategic experience with emulation platforms such as Palladium, Zebu, or Veloce for software integration and system-level test acceleration.
• Experience defining verification roadmaps, conducting code reviews, and mentoring senior engineering staff.

Nice to have

• Master’s degree or Ph.D. in Electrical Engineering or Computer Science.
• Exposure to or hands-on experience implementing AI and Machine Learning techniques in verification pipelines, including stimulus generation, coverage convergence, bug triage, or regression optimization.
• Experience with high-speed interfaces such as PCIe Gen6/7, CXL, HBM3, or NVLink.
• Experience managing globally distributed engineering teams.

Culture & Benefits

• Health and wellbeing benefits supporting physical, financial, and emotional wellbeing.
• Personal and professional development programs supporting career growth and specialization.
• Inclusive workplace committed to accessibility and equal employment opportunity.
• Flexibility to manage work and personal needs within the onsite role structure.