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5 дней назад

Design Verification Manager (Semiconductor)

174 000 - 352 500$
Формат работы
onsite
Тип работы
fulltime
Грейд
lead
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Design Verification Manager (Semiconductor): Leading silicon verification teams and defining advanced verification strategies for high-performance SoC and IP products with an accent on UVM testbench architecture, formal verification, and emulation. Focus on scaling engineering teams, closing coverage gaps, debugging system-level failures, and delivering zero-bug tape-outs.

Location: Onsite, with an expectation to primarily work from an HPE office; salary information is specified for the United States of America in California.

Salary: USD 174,000–352,500 annual base salary in California, United States. Variable incentives may also be offered.

Company

hirify.global is a global edge-to-cloud technology company developing solutions that connect, protect, analyze, and operate on data and applications.

What you will do

  • Lead, mentor, and grow a team of design verification engineers while fostering technical excellence and accountability.
  • Allocate engineering resources across multiple parallel chip and block schedules.
  • Define verification strategies, infrastructure, and execution plans for complex SoC and IP blocks.
  • Own testbench architecture from initial specifications through structural sign-off.
  • Drive functional metric tracking, automated verification flows, and block, subsystem, and full-chip environments.
  • Collaborate with Architecture, RTL Design, Physical Design, and Post-Silicon Validation teams to close coverage gaps, debug failures, and meet tape-out milestones.

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Science, Computer Engineering, or a closely related technical field.
  • 10+ years of hands-on pre-silicon ASIC/SoC design verification experience.
  • 5+ years of engineering management or formal team leadership experience, including engineering headcount management, performance reviews, and project delivery schedules.
  • Expert-level SystemVerilog and UVM architecture expertise.
  • Experience building scalable UVM-compliant testbenches from scratch.
  • Hands-on experience with formal verification and emulation or hardware acceleration platforms such as Palladium, Zebu, or Veloce.

Nice to have

  • Master’s degree or Ph.D. in Electrical Engineering or Computer Science.
  • Experience applying AI/ML to stimulus generation, coverage convergence, bug triage, or regression optimization.
  • Experience with high-speed interfaces such as PCIe Gen6/7, CXL, HBM3, or NVLink.
  • Experience managing globally distributed engineering teams.

Culture & Benefits

  • Health, financial, and emotional wellbeing benefits for employees and their families.
  • Programs supporting personal and professional development and career progression.
  • Inclusive work environment that values varied backgrounds and individual uniqueness.
  • Flexibility to manage work and personal needs within the onsite role structure.

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