Technical Staff Engineer-Design (SoC)

Location: Neu-Ulm, Germany

Company

hirify.global is a global semiconductor company developing technologies and products for embedded and wireless applications.

What you will do

• Contribute to wireless SoC design from concept through tape-out.
• Implement RTL designs from micro-architecture specifications using Verilog and SystemVerilog.
• Execute synthesis, timing constraint, timing analysis, and ASIC design-flow activities.
• Collaborate with verification, analog, validation, software, and physical design teams across international sites.
• Support silicon qualification, validation, and debugging of IC issues.
• Develop and optimize low-power design techniques and power-estimation methodologies.

Requirements

• Bachelor’s degree in computer engineering, electrical engineering, or a related field.
• At least 12 years of experience in digital SoC design, especially low-power design.
• Proficiency in RTL design, Verilog/SystemVerilog, synthesis, SDC timing constraints, and timing analysis.
• Experience with ASIC design flows, including LINT, formal verification, CDC/RDC, power estimation, MBIST/DFT concepts, and low-power techniques.
• Knowledge of SoC architectures such as ARM/MIPS, AMBA and AXI bus protocols, peripheral IPs, and bus matrix design.
• Excellent English reading, writing, and verbal communication skills are required.

Nice to have

• Master’s degree in computer engineering, electrical engineering, or a related field.
• Knowledge of Bluetooth/BLE and Wi-Fi communication theory and specifications.
• Knowledge of security features and functional-safety-compliant design principles.
• Experience with UVM/OVM verification and FPGA or silicon-board validation.

Culture & Benefits

• Full-time role within a large international semiconductor organization.
• Collaboration with international design and implementation teams.
• Opportunity to contribute to high-performance, low-power wireless technologies.
• Travel expectation of 0%–25%.