Microarchitect and RTL Design Engineer

Location: Santa Clara, California, United States

Company

hirify.global is a Series B semiconductor startup developing and licensing software-driven unified fabric intellectual property for single-die and multi-die systems in the chiplet era.

What you will do

• Design and develop highly configurable IP microarchitectures.
• Write microarchitecture specifications and RTL focused on performance, power, and area optimization.
• Collaborate with software teams to define configuration requirements and verification collateral.
• Work with verification teams on assertions, test plans, debugging, and coverage.

Requirements

• 8+ years of current, hands-on experience in microarchitecture and RTL development.
• Bachelor’s or master’s degree in electrical engineering, computer engineering, or computer science.
• Proficiency in Verilog and SystemVerilog.
• Experience with industry-standard EDA tools and methodologies.
• Experience with large high-speed pipelined and stateful designs, low-power designs, on-chip interconnects, and NoCs.
• Experience with Arm ACE/CHI or similar coherency protocols, including IP blocks for caches, cache coherency, memory subsystems, interconnects, and NoCs.

Nice to have

• Experience with RAS designs, QoS in fabrics, and PCIe/IO.
• Experience with modern programming languages such as Python.

Culture & Benefits

• Performance incentives.
• Comprehensive medical, dental, and vision benefits.
• 401(k) retirement plan.
• Equity.
• Work on semiconductor IP supporting data center, infrastructure, AI, automotive, and Edge IoT applications.