Lead Digital Design Engineer (UCIe)

Company

hirify.global is a well-funded startup building critical photonics infrastructure and optical interconnects for AI supercomputing.

What you will do

• Define digital front-end micro-architecture and block partitioning for first-of-its-kind chiplets.
• Own the high-speed datapath, including UCIe streaming adapters, elastic FIFOs, and custom logic.
• Establish front-end design methodology, including RTL coding standards, lint, and CDC/RDC signoff.
• Collaborate with physical design teams on timing-aware micro-architecture and floorplanning.
• Lead, grow, and mentor the front-end design team as the organization scales.
• Define clocking, reset, and low-power architecture including UPF power intent.

Requirements

• 10+ years of experience in digital design and micro-architecture.
• Proven lead ownership of high-throughput datapath or SerDes-adjacent SoC projects.
• Strong expertise in SystemVerilog RTL and timing-aware design at multi-hundred-Gbps rates.
• Deep understanding of UCIe, PCIe, or CXL interface architectures.
• Experience with scale-up vs. scale-out interconnect architectures.
• Must be based in San Jose, CA.

Nice to have

• Experience with FEC/coding datapath (e.g., Reed-Solomon).
• Background in optical transceivers, CPO, or linear-drive optics.
• Advanced-node (N5/N3/N2) design experience.

Culture & Benefits

• Competitive salary and comprehensive benefits package including health, dental, and vision.
• Access to cutting-edge technology and cloud platforms.
• Professional development opportunities and certification support.
• Collaborative work environment with world-class engineering teams.