Package & SI/PI - Senior/Staff Packaging Engineer - Electro-Thermal

Location: Bay Area, United States; on-site Monday through Friday.

Company

hirify.global is a chiplet interconnect startup developing advanced semiconductor packaging and heterogeneous integration technologies.

What you will do

• Develop steady-state and transient thermal models for 2.5D/3D IC packages, chiplets, and multi-die systems, including hotspot identification.
• Perform power integrity, IR drop, electromigration, and reliability analysis for PDNs, interconnects, bumps, TSVs, and redistribution layers.
• Build chip-package co-simulation workflows with ANSYS and Cadence EDA tools, including RedHawk-SC, RHSC Electrothermal, SIwave, Sigrity, and Clarity.
• Create compact macro models and reduced-order thermal models for early-stage design optimization.
• Automate simulation workflows and design-space exploration using Python, C/C++, Tcl, Shell, and verification languages.
• Collaborate with silicon, package design, product, and manufacturing teams on design-for-reliability initiatives and customer technical engagements.

Requirements

• PhD in Electrical or Mechanical Engineering, or a related field focused on thermal management, power delivery, or electronic packaging; a Master's degree with 5+ years of experience may be considered.
• Strong background in power integrity, signal integrity, thermal management, EM/IR analysis, thermal physics, and electrothermal co-simulation.
• Expertise with EDA tools including ANSYS RedHawk-SC, RHSC Electrothermal, Totem, PathFinder, SIwave, HFSS, Q3D, Cadence Voltus, Sigrity, Clarity, Synopsys RedHawk Fusion, PrimeTime, and ICC2.
• Experience with physical design tools, RTL-to-GDSII flows, and programming or scripting in Python, C/C++, Tcl, Shell, and Verilog, VHDL, or SystemVerilog.
• Knowledge of 2.5D/3D ICs, CoWoS, InFO, EMIB, chiplets, TSVs, interposers, FOWLP, RDL design, UCIe, BoW, die-to-die interfaces, and wafer-scale integration.
• Hands-on experience with semiconductor package thermal/electrical analysis and tape-outs, plus understanding of heat transfer, thermal materials, and CTE mismatch.

Nice to have

• Machine learning applications in EDA and design optimization.
• HPC, AI/ML accelerator packaging, or co-packaged optics experience.
• Reliability testing experience, including thermal cycling, HTOL, THB, and measurement correlation.

Culture & Benefits

• Full-time, on-site work in the Bay Area, Monday through Friday.
• Fast-paced environment with opportunities for cross-functional collaboration and independent problem-solving.
• Excellent benefits and a work environment focused on innovation and advanced packaging.