9 часов назад
Senior IC Packaging Engineer
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Senior IC Packaging Engineer (Advanced Semiconductor Packaging): Defining and driving high-performance, low-power IC and System-in-Package architectures across 2D, 2.5D RDL fan-out, chiplet, and heterogeneous integration designs with an accent on package architecture, high-speed interfaces, and manufacturing readiness. Focus on leading end-to-end packaging programs, balancing signal, power, thermal, mechanical, reliability, cost, and yield requirements, and collaborating with foundries, OSATs, and substrate suppliers.
Location: Ho Chi Minh City, Vietnam
Company
develops secure AI-powered digital infrastructure based on its Trusted Control/Compute Unit semiconductor technology.
What you will do
- Provide technical leadership and architectural ownership for IC and System-in-Package packaging across multiple products and programs.
- Define package architectures and technology roadmaps spanning 2D, RDL-based fan-out 2.5D, chiplet, and heterogeneous integration designs.
- Lead chiplet packaging strategies involving UCIe, silicon interposers, advanced RDL, bump architectures, and substrate stack-ups.
- Guide hands-on package design and physical layout for high-speed SerDes/PHY, PCIe, CXL, LPDDR5, UCIe, and other multi-gigabit interfaces.
- Drive signal integrity, power integrity, thermal, mechanical, reliability, DFM, cost, yield, schedule, and risk trade-offs.
- Coordinate technology development and manufacturing readiness with foundries, OSATs, substrate suppliers, and cross-functional teams.
Requirements
- BSEE or MSEE in Electrical Engineering or a related field; PhD is a plus.
- 10+ years of extensive IC packaging experience for SoCs, ASICs, or memory products.
- Deep hands-on expertise in flip-chip BGA, System-in-Package, RDL, silicon interposers, and UCIe chiplet architectures.
- Experience leading end-to-end packaging programs from early architecture through high-volume production.
- Experience with high-speed SerDes package development, including PCIe Gen5, LPDDR5/LPDDR5X, USB 3.x, or 10G interfaces.
- Strong cross-functional leadership and direct collaboration with OSATs, foundries, substrate suppliers, design, product, test, operations, reliability, and customer teams.
Nice to have
- Experience with Cadence Allegro Package Designer or equivalent EDA tools.
- SI/PI expertise, including S-parameter extraction and PDN optimization with HFSS, SIwave, or Ansys Designer.
- Experience building packaging methodologies or platforms from scratch.
- PhD in Electrical Engineering or a related field.
Culture & Benefits
- Fast-growing startup environment focused on silicon, systems, AI, and security innovation.
- Work alongside teams developing technology for data centers, cloud platforms, and AI infrastructure.
- Culture emphasizing curiosity, execution, respect, continuous learning, and practical problem-solving.
- Diverse and multifaceted work environment with cross-functional collaboration.
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